From mboxrd@z Thu Jan  1 00:00:00 1970
Received: from eggs.gnu.org ([2001:4830:134:3::10]:49366)
	by lists.gnu.org with esmtp (Exim 4.71)
	(envelope-from <peter.maydell@linaro.org>) id 1ZZE8O-0003fP-Jt
	for qemu-devel@nongnu.org; Tue, 08 Sep 2015 04:20:09 -0400
Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)
	(envelope-from <peter.maydell@linaro.org>) id 1ZZE8J-0002Ce-Vc
	for qemu-devel@nongnu.org; Tue, 08 Sep 2015 04:20:08 -0400
Received: from mail-yk0-f176.google.com ([209.85.160.176]:33831)
	by eggs.gnu.org with esmtp (Exim 4.71)
	(envelope-from <peter.maydell@linaro.org>) id 1ZZE8J-0002CU-Si
	for qemu-devel@nongnu.org; Tue, 08 Sep 2015 04:20:03 -0400
Received: by ykdg206 with SMTP id g206so107491515ykd.1
	for <qemu-devel@nongnu.org>; Tue, 08 Sep 2015 01:20:03 -0700 (PDT)
MIME-Version: 1.0
In-Reply-To: <55EE6F99.9040309@twiddle.net>
References: <1441216660-8717-1-git-send-email-rth@twiddle.net>
	<1441216660-8717-6-git-send-email-rth@twiddle.net>
	<CAFEAcA_JxkqqD3E25a3a5YqKinxJHb22Q4JC9oA51swdU-txJw@mail.gmail.com>
	<55EE6F99.9040309@twiddle.net>
From: Peter Maydell <peter.maydell@linaro.org>
Date: Tue, 8 Sep 2015 09:19:43 +0100
Message-ID: <CAFEAcA9KUzL+LMzYmhpnEhWZvz3paT_tCtMHHFiLd9CFyRoE-g@mail.gmail.com>
Content-Type: text/plain; charset=UTF-8
Subject: Re: [Qemu-devel] [PATCH v2 05/11] target-arm: Implement ccmp
	branchless
List-Id: <qemu-devel.nongnu.org>
List-Unsubscribe: <https://lists.nongnu.org/mailman/options/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>
List-Archive: <http://lists.nongnu.org/archive/html/qemu-devel>
List-Post: <mailto:qemu-devel@nongnu.org>
List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help>
List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=subscribe>
To: Richard Henderson <rth@twiddle.net>
Cc: QEMU Developers <qemu-devel@nongnu.org>

On 8 September 2015 at 06:18, Richard Henderson <rth@twiddle.net> wrote:
> On 09/07/2015 10:31 AM, Peter Maydell wrote:
>>>
>>> -    if (cond < 0x0e) { /* continue */
>>> -        gen_set_label(label_continue);
>>> +    /* If COND was false, force the flags to #nzcv.
>>> +       Note that T1 = (COND ? 0 : -1), T2 = (COND ? -1 : 0).  */
>>> +    tcg_t1 = tcg_temp_new_i32();
>>> +    tcg_t2 = tcg_temp_new_i32();
>>> +    tcg_gen_neg_i32(tcg_t1, tcg_t0);
>>> +    tcg_gen_subi_i32(tcg_t2, tcg_t0, 1);
>>
>>
>> t2 is ~t1, right? Do we get better/worse code if we use
>> tcg_gen_andc_i32(..., tcg_t1) rather than creating t2 and
>> using gen_and_i32 ?
>>
>>> +
>>> +    if (nzcv & 8) { /* N */
>>> +        tcg_gen_or_i32(cpu_NF, cpu_NF, tcg_t1);
>>> +    } else {
>>> +        tcg_gen_and_i32(cpu_NF, cpu_NF, tcg_t2);
>>> +    }
>>> +    if (nzcv & 4) { /* Z */
>>> +        tcg_gen_and_i32(cpu_ZF, cpu_ZF, tcg_t2);
>>> +    } else {
>>> +        tcg_gen_or_i32(cpu_ZF, cpu_ZF, tcg_t0);
>>> +    }
>>> +    if (nzcv & 2) { /* C */
>>> +        tcg_gen_or_i32(cpu_CF, cpu_CF, tcg_t0);
>>> +    } else {
>>> +        tcg_gen_and_i32(cpu_CF, cpu_CF, tcg_t2);
>>> +    }
>>> +    if (nzcv & 1) { /* V */
>>> +        tcg_gen_or_i32(cpu_VF, cpu_VF, tcg_t1);
>>> +    } else {
>>> +        tcg_gen_and_i32(cpu_VF, cpu_VF, tcg_t2);
>
>
> If the host supports andc, it's probably better to use only the one temp.
> But otherwise we may save 4 not insns.

The tcg common code isn't smart enough to notice it only
needs to calculate not(t1) once ?

In the overwhelmingly common case (x86 tcg backend)
we would save an insn every time, right?

>  Is it worth complicating the code
> for that?

I wouldn't bother to make the front-end generate different
code for the backend does/doesn't have andc situations,
certainly.

Anyway, I'm just guessing here, you probably have a better
feel than me for what codegen choices work better, so I'll
leave the choice up to you.

thanks
-- PMM