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From: Peter Maydell <peter.maydell@linaro.org>
To: Francisco Iglesias <francisco.iglesias@amd.com>
Cc: qemu-devel@nongnu.org, frasse.iglesias@gmail.com,
	alistair@alistair23.me,  edgar.iglesias@gmail.com,
	fkonrad@amd.com, sai.pavan.boddu@amd.com,  tong.ho@amd.com,
	vikram.garhwal@amd.com
Subject: Re: [PATCH v1 6/8] hw/misc: Introduce a model of Xilinx Versal's CFRAME_BCAST_REG
Date: Thu, 3 Aug 2023 15:04:03 +0100	[thread overview]
Message-ID: <CAFEAcA9OGCPm1F3AvcAJs33YBrMisi0AubJQANZKjWxSQw6+hw@mail.gmail.com> (raw)
In-Reply-To: <20230710140249.56324-7-francisco.iglesias@amd.com>

On Mon, 10 Jul 2023 at 15:03, Francisco Iglesias
<francisco.iglesias@amd.com> wrote:
>
> Introduce a model of Xilinx Versal's Configuration Frame broadcast
> controller (CFRAME_BCAST_REG).
>
> Signed-off-by: Francisco Iglesias <francisco.iglesias@amd.com>
> ---
>  hw/misc/xlnx-versal-cframe-reg.c         | 173 +++++++++++++++++++++++
>  include/hw/misc/xlnx-versal-cframe-reg.h |  17 +++
>  2 files changed, 190 insertions(+)

Missing reset again.

> +static uint64_t cframes_bcast_reg_read(void *opaque, hwaddr addr, unsigned size)
> +{
> +    qemu_log_mask(LOG_GUEST_ERROR, "%s: Unsupported read from addr=%"
> +                  HWADDR_PRIx "\n", __func__, addr);
> +    return 0;
> +}
> +
> +static void cframes_bcast_reg_write(void *opaque, hwaddr addr, uint64_t value,
> +                      unsigned size)
> +{
> +    XlnxVersalCFrameBcastReg *s = XLNX_VERSAL_CFRAME_BCAST_REG(opaque);
> +    unsigned int idx;
> +
> +    /* 4 32bit words. */
> +    idx = (addr >> 2) & 3;
> +
> +    s->wfifo[idx] = value;
> +
> +    /* Writing to the top word triggers the transmit onto CFI. */
> +    if (idx == 3) {
> +        uint32_t reg_addr = extract32(addr, 4, 6);
> +        XlnxCfiPacket pkt = {
> +            .reg_addr = reg_addr,
> +            .data[0] = s->wfifo[0],
> +            .data[1] = s->wfifo[1],
> +            .data[2] = s->wfifo[2],
> +            .data[3] = s->wfifo[3]
> +        };
> +
> +        for (int i = 0; i < ARRAY_SIZE(s->cfg.cframe); i++) {
> +            if (s->cfg.cframe[i]) {
> +                xlnx_cfi_transfer_packet(s->cfg.cframe[i], &pkt);
> +            }
> +        }
> +
> +        memset(s->wfifo, 0, 4 * sizeof(uint32_t));
> +    }
> +}

> +static void cframes_bcast_fdri_write(void *opaque, hwaddr addr, uint64_t value,
> +                      unsigned size)
> +{
> +    XlnxVersalCFrameBcastReg *s = XLNX_VERSAL_CFRAME_BCAST_REG(opaque);
> +    unsigned int idx;
> +
> +    /* 4 32bit words. */
> +    idx = (addr >> 2) & 3;
> +
> +    s->wfifo[idx] = value;
> +
> +    /* Writing to the top word triggers the transmit onto CFI. */
> +    if (idx == 3) {
> +        XlnxCfiPacket pkt = {
> +            .reg_addr = CFRAME_FDRI,
> +            .data[0] = s->wfifo[0],
> +            .data[1] = s->wfifo[1],
> +            .data[2] = s->wfifo[2],
> +            .data[3] = s->wfifo[3]
> +        };
> +
> +        for (int i = 0; i < ARRAY_SIZE(s->cfg.cframe); i++) {
> +            if (s->cfg.cframe[i]) {
> +                xlnx_cfi_transfer_packet(s->cfg.cframe[i], &pkt);
> +            }
> +        }
> +
> +        memset(s->wfifo, 0, 4 * sizeof(uint32_t));
> +    }
> +}

I feel like I've seen this code structure in several patches:
opportunity to share code ?

thanks
-- PMM


  reply	other threads:[~2023-08-03 14:04 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-07-10 14:02 [PATCH v1 0/8] Xilinx Versal CFI support Francisco Iglesias
2023-07-10 14:02 ` [PATCH v1 1/8] hw/misc: Introduce the Xilinx CFI interface Francisco Iglesias
2023-07-12  5:37   ` Boddu, Sai Pavan
2023-07-10 14:02 ` [PATCH v1 2/8] hw/misc: Introduce a model of Xilinx Versal's CFU_APB Francisco Iglesias
2023-08-03 13:32   ` Peter Maydell
2023-07-10 14:02 ` [PATCH v1 3/8] hw/misc/xlnx-versal-cfu: Introduce a model of Xilinx Versal CFU_FDRO Francisco Iglesias
2023-08-03 13:48   ` Peter Maydell
2023-08-10 19:15     ` Francisco Iglesias
2023-07-10 14:02 ` [PATCH v1 4/8] hw/misc/xlnx-versal-cfu: Introduce a model of Xilinx Versal's CFU_SFR Francisco Iglesias
2023-08-03 13:49   ` Peter Maydell
2023-07-10 14:02 ` [PATCH v1 5/8] hw/misc: Introduce a model of Xilinx Versal's CFRAME_REG Francisco Iglesias
2023-08-03 14:01   ` Peter Maydell
2023-07-10 14:02 ` [PATCH v1 6/8] hw/misc: Introduce a model of Xilinx Versal's CFRAME_BCAST_REG Francisco Iglesias
2023-08-03 14:04   ` Peter Maydell [this message]
2023-07-10 14:02 ` [PATCH v1 7/8] hw/arm/xlnx-versal: Connect the CFU_APB, CFU_FDRO and CFU_SFR Francisco Iglesias
2023-08-03 13:50   ` Peter Maydell
2023-07-10 14:02 ` [PATCH v1 8/8] hw/arm/versal: Connect the CFRAME_REG and CFRAME_BCAST_REG Francisco Iglesias
2023-08-03 13:52   ` Peter Maydell
2023-07-12 12:20 ` [PATCH v1 0/8] Xilinx Versal CFI support Edgar E. Iglesias

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