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Wed, 29 Oct 2025 07:03:21 -0700 (PDT) MIME-Version: 1.0 References: <20251014200718.422022-1-richard.henderson@linaro.org> <20251014200718.422022-25-richard.henderson@linaro.org> <3cdafcc5-dc91-4612-b53b-8b6ad92de7b2@linaro.org> In-Reply-To: <3cdafcc5-dc91-4612-b53b-8b6ad92de7b2@linaro.org> From: Peter Maydell Date: Wed, 29 Oct 2025 14:03:08 +0000 X-Gm-Features: AWmQ_bkbdc526swJFCPWOz3iQfiOLz8-lnTCZf_5aVV1P3e70AWvfkCr6K22T3s Message-ID: Subject: Re: [PATCH v2 24/37] target/arm: Use flush_if_asid_change in vmsa_ttbr_write To: Richard Henderson Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::b134; envelope-from=peter.maydell@linaro.org; helo=mail-yx1-xb134.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Wed, 29 Oct 2025 at 13:14, Richard Henderson wrote: > > On 10/20/25 16:08, Peter Maydell wrote: > > On Tue, 14 Oct 2025 at 21:17, Richard Henderson > > wrote: > >> > >> Only flush the subset of tlbs that are affected by the ttbr > >> register to which we are writing. > >> > >> Signed-off-by: Richard Henderson > >> --- > >> target/arm/helper.c | 19 ++++++++++++++----- > >> 1 file changed, 14 insertions(+), 5 deletions(-) > >> > >> diff --git a/target/arm/helper.c b/target/arm/helper.c > >> index c6d290ce7c..2b55e219c2 100644 > >> --- a/target/arm/helper.c > >> +++ b/target/arm/helper.c > >> @@ -2943,11 +2943,20 @@ static void flush_if_asid_change(CPUARMState *env, const ARMCPRegInfo *ri, > >> static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, > >> uint64_t value) > >> { > >> - /* If the ASID changes (with a 64-bit write), we must flush the TLB. */ > >> - if (cpreg_field_type(ri) == MO_64 && > >> - extract64(raw_read(env, ri) ^ value, 48, 16) != 0) { > >> - ARMCPU *cpu = env_archcpu(env); > >> - tlb_flush(CPU(cpu)); > >> + /* > >> + * If the ASID changes (with a 64-bit write), we must flush the TLB. > >> + * The non-secure ttbr registers affect the EL1 regime; > >> + * the secure ttbr registers affect the AA32 EL3 regime. > >> + */ > >> + if (cpreg_field_type(ri) == MO_64) { > >> + flush_if_asid_change(env, ri, value, > >> + ri->secure & ARM_CP_SECSTATE_S > >> + ? (ARMMMUIdxBit_E30_0 | > >> + ARMMMUIdxBit_E30_3_PAN | > >> + ARMMMUIdxBit_E3) > >> + : (ARMMMUIdxBit_E10_1 | > >> + ARMMMUIdxBit_E10_1_PAN | > >> + ARMMMUIdxBit_E10_0)); > >> } > > > > What's the value of ri->secure here for the case where EL3 is > > AArch64 and we're in Secure EL1 at AArch32 ? > > Um.. the state of the cpu doesn't apply. > ri->secure is true only for TTBR[01]_S. > > I'm not sure what the question is? If you get into this function because of a TTBR write executed at Secure EL1 AArch32 (where EL3 is AArch64), what is ri->secure ? That is, do we correctly flush for the EL1 mmuidx, or is ri->secure true and we wrongly flush EL3 ? (For EL3 == AArch32 a TTBR write in a Secure PL should flush for the EL3 mmuidx values.) -- PMM