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From: Peter Maydell <peter.maydell@linaro.org>
To: Richard Henderson <richard.henderson@linaro.org>
Cc: qemu-arm <qemu-arm@nongnu.org>, QEMU Developers <qemu-devel@nongnu.org>
Subject: Re: [Qemu-devel] [PATCH 1/2] target/arm: Allow ARMCPRegInfo read/write functions to throw exceptions
Date: Tue, 27 Aug 2019 15:47:56 +0100	[thread overview]
Message-ID: <CAFEAcA9VoFNSLmPgosPat4GAyC50uDq7aeUeyvZ7D_1CoEHRoA@mail.gmail.com> (raw)
In-Reply-To: <750250d4-e4a0-43de-add5-24488b87cfea@linaro.org>

On Sun, 18 Aug 2019 at 07:12, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> On 8/16/19 1:58 PM, Peter Maydell wrote:
> > @@ -1729,6 +1729,12 @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
> >          tcg_temp_free_ptr(tmpptr);
> >          tcg_temp_free_i32(tcg_syn);
> >          tcg_temp_free_i32(tcg_isread);
> > +    } else if (ri->type & ARM_CP_RAISES_EXC) {
> > +        /*
> > +         * The readfn or writefn might raise an exception;
> > +         * synchronize the CPU state in case it does.
> > +         */
> > +        gen_a64_set_pc_im(s->pc - 4);
>
> This will now need an update for master, but otherwise,
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Thanks; applied series to target-arm.next with this squashed
in to handle the changes in master:

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index b3053d3fb89..4d09ae6f424 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -1719,7 +1719,7 @@ static void handle_sys(DisasContext *s, uint32_t
insn, bool isread,
          * The readfn or writefn might raise an exception;
          * synchronize the CPU state in case it does.
          */
-        gen_a64_set_pc_im(s->pc - 4);
+        gen_a64_set_pc_im(s->pc_curr);
     }

     /* Handle special cases first */
diff --git a/target/arm/translate.c b/target/arm/translate.c
index adb97dc6a3d..78d93f63cab 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -7197,7 +7197,7 @@ static int disas_coproc_insn(DisasContext *s,
uint32_t insn)
              * synchronize the CPU state in case it does.
              */
             gen_set_condexec(s);
-            gen_set_pc_im(s, s->pc - 4);
+            gen_set_pc_im(s, s->pc_curr);
         }

         /* Handle special cases first */


-- PMM


  reply	other threads:[~2019-08-27 14:49 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-08-16 12:58 [Qemu-devel] [PATCH 0/2] target/arm: Take exceptions on ATS instructions Peter Maydell
2019-08-16 12:58 ` [Qemu-devel] [PATCH 1/2] target/arm: Allow ARMCPRegInfo read/write functions to throw exceptions Peter Maydell
2019-08-18  6:12   ` Richard Henderson
2019-08-27 14:47     ` Peter Maydell [this message]
2019-08-16 12:58 ` [Qemu-devel] [PATCH 2/2] target/arm: Take exceptions on ATS instructions when needed Peter Maydell
2019-08-18  6:23   ` Richard Henderson
2019-08-16 18:13 ` [Qemu-devel] [PATCH 0/2] target/arm: Take exceptions on ATS instructions no-reply
2019-08-19 12:44 ` Peter Maydell
2019-08-19 17:33   ` Edgar E. Iglesias
2019-08-20 12:59   ` Edgar E. Iglesias

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