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bh=5tVPVNzDALYzakMPqGGCIzYb1I80NK4X5006/rlAVmI=; b=CWfOpPVGgKTewIC0i+Nqc4AAngKYm8Otj4Z2OhgHT9ECYiTZZVyjijss6zQAmlv4iX bv2BG1+Kj7FTiowD4kd99VqFWLOrxfFibW4x/VDKpr2Puvw7qx36kS/NBv30OWHsUtTA A3IWBBYbXsZYmYkzzaSMMyUWfTfuJy2WbMN+tggzTbv45zWbLjZ2GK9XOT2Y4xwTDzwt +Y22oZB39yimP3zzXUgBtkztzx0IUlnIIk7ofTUPfavTgtAKhIF4H/LqQE7v3WPw93YT OsS4V781xq3B0ZaQi1lE1IELTSfJjl48VX1kJfCNP6fTMAZCBA7/o5XWls3Fo/o7CrNb gYdw== X-Gm-Message-State: AC+VfDwcamPZfnandGTigxTQUvNvSaTI56FxlpAaqge5yxSA1ElancXV fcxZc0/NnZpqi9TdnE+qG+BB39/2yXLHAZpZlDexag== X-Google-Smtp-Source: ACHHUZ7jjAI+a0ktR8aZM4g5wU2nnGAx4wld0DByEChZv4ZYLFvdP/sEl80EEHfxzEKcIjASq0GJuzTf6blFdtBwrPI= X-Received: by 2002:a50:fb96:0:b0:504:b511:1a39 with SMTP id e22-20020a50fb96000000b00504b5111a39mr1416085edq.12.1683292674989; Fri, 05 May 2023 06:17:54 -0700 (PDT) MIME-Version: 1.0 References: <20230503070656.1746170-1-richard.henderson@linaro.org> <20230503070656.1746170-48-richard.henderson@linaro.org> In-Reply-To: <20230503070656.1746170-48-richard.henderson@linaro.org> From: Peter Maydell Date: Fri, 5 May 2023 14:17:44 +0100 Message-ID: Subject: Re: [PATCH v4 47/57] tcg/mips: Use atom_and_align_for_opc To: Richard Henderson Cc: qemu-devel@nongnu.org, git@xen0n.name, gaosong@loongson.cn, philmd@linaro.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::534; envelope-from=peter.maydell@linaro.org; helo=mail-ed1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Wed, 3 May 2023 at 08:41, Richard Henderson wrote: > > Signed-off-by: Richard Henderson > --- > tcg/mips/tcg-target.c.inc | 11 ++++++++--- > 1 file changed, 8 insertions(+), 3 deletions(-) > > diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc > index cd0254a0d7..43a8ffac17 100644 > --- a/tcg/mips/tcg-target.c.inc > +++ b/tcg/mips/tcg-target.c.inc > @@ -1139,6 +1139,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) > typedef struct { > TCGReg base; > MemOp align; > + MemOp atom; > } HostAddress; > > bool tcg_target_has_memory_bswap(MemOp memop) > @@ -1158,11 +1159,16 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, > { > TCGLabelQemuLdst *ldst = NULL; > MemOp opc = get_memop(oi); > - unsigned a_bits = get_alignment_bits(opc); > + MemOp a_bits, atom_u; > unsigned s_bits = opc & MO_SIZE; > - unsigned a_mask = (1 << a_bits) - 1; > + unsigned a_mask; > TCGReg base; > > + a_bits = atom_and_align_for_opc(s, &h->atom, &atom_u, opc, > + MO_ATOM_IFALIGN, false); > + h->align = a_bits; > + a_mask = (1 << a_bits) - 1; > + > #ifdef CONFIG_SOFTMMU > unsigned s_mask = (1 << s_bits) - 1; > int mem_index = get_mmuidx(oi); Reviewed-by: Peter Maydell (For a set of functions so new they're not even in master yet these do seem to have a surprisingly large variance in how they're setting up these HostAddress structs...) thanks -- PMM