From: Peter Maydell <peter.maydell@linaro.org>
To: Palmer Dabbelt <palmerdabbelt@google.com>
Cc: Alistair Francis <alistair.francis@wdc.com>,
"open list:RISC-V" <qemu-riscv@nongnu.org>,
QEMU Developers <qemu-devel@nongnu.org>
Subject: Re: [PULL] RISC-V Patches for 5.0-rc4
Date: Tue, 21 Apr 2020 20:27:50 +0100 [thread overview]
Message-ID: <CAFEAcA9ZrLDnU1KLmoPBqhS1fYVG05TzN3bojEGherL7PRhwFg@mail.gmail.com> (raw)
In-Reply-To: <20200421191001.92644-1-palmerdabbelt@google.com>
On Tue, 21 Apr 2020 at 20:19, Palmer Dabbelt <palmerdabbelt@google.com> wrote:
> ----------------------------------------------------------------
> RISC-V Patches for 5.0-rc4
>
> This contains handful of patches that I'd like to target for 5.0. I know it's
> a bit late, I thought I'd already sent these out but must have managed to miss
> doing so. The patches include:
>
> * A handful of fixes to PTE lookups related to H-mode support.
> * The addition of a serial number fo the SiFive U implementetaion, which allows
> bootloaders to generate a sane MAC address.
>
> These pass "make check" and boot Linux for me.
>
> ----------------------------------------------------------------
> Peter: Sorry I dropped the ball here. I can understand if it's too late for
> 5.0, but if there's still going to be an rc4 then I'd love to have these
> included.
> ----------------------------------------------------------------
Nope, sorry. rc4 has technically not been tagged yet, but especially
the serial-property stuff is too big a code change at this point
(it includes one "let's just refactor and rearrange some code"
patch which is really not rc4 material.)
Also these patches have been on the list for over a month -- if
they were 5.0-worthy there's been plenty of time for them to be
put in.
Plus the last email from Alistair on the "target/riscv: Don't set
write permissions on dirty PTEs" patch thread is a note saying
it shouldn't be applied, unless I've got confused.
thanks
-- PMM
next prev parent reply other threads:[~2020-04-21 19:29 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-21 19:09 [PULL] RISC-V Patches for 5.0-rc4 Palmer Dabbelt
2020-04-21 19:09 ` [PULL 1/6] target/riscv: Don't set write permissions on dirty PTEs Palmer Dabbelt
2020-04-21 19:20 ` Alistair Francis
2020-04-21 19:09 ` [PULL 2/6] riscv: Don't use stage-2 PTE lookup protection flags Palmer Dabbelt
2020-04-21 19:09 ` [PULL 3/6] riscv: AND stage-1 and stage-2 " Palmer Dabbelt
2020-04-21 19:09 ` [PULL 4/6] riscv/sifive_u: Fix up file ordering Palmer Dabbelt
2020-04-21 19:10 ` [PULL 5/6] riscv/sifive_u: Add a serial property to the sifive_u SoC Palmer Dabbelt
2020-04-21 19:10 ` [PULL 6/6] riscv/sifive_u: Add a serial property to the sifive_u machine Palmer Dabbelt
2020-04-21 19:27 ` Peter Maydell [this message]
2020-04-21 19:32 ` [PULL] RISC-V Patches for 5.0-rc4 Palmer Dabbelt
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