* [PULL 1/6] target/riscv: Don't set write permissions on dirty PTEs
2020-04-21 19:09 [PULL] RISC-V Patches for 5.0-rc4 Palmer Dabbelt
@ 2020-04-21 19:09 ` Palmer Dabbelt
2020-04-21 19:20 ` Alistair Francis
2020-04-21 19:09 ` [PULL 2/6] riscv: Don't use stage-2 PTE lookup protection flags Palmer Dabbelt
` (5 subsequent siblings)
6 siblings, 1 reply; 10+ messages in thread
From: Palmer Dabbelt @ 2020-04-21 19:09 UTC (permalink / raw)
To: Peter Maydell
Cc: qemu-riscv, qemu-devel, Alistair Francis, Bin Meng,
Palmer Dabbelt
From: Alistair Francis <alistair.francis@wdc.com>
The RISC-V spec specifies that when a write happens and the D bit is
clear the implementation will set the bit in the PTE. It does not
describe that the PTE being dirty means that we should provide write
access. This patch removes the write access granted to pages when the
dirty bit is set.
Following the prot variable we can see that it affects all of these
functions:
riscv_cpu_tlb_fill()
tlb_set_page()
tlb_set_page_with_attrs()
address_space_translate_for_iotlb()
Looking at the cputlb code (tlb_set_page_with_attrs() and
address_space_translate_for_iotlb()) it looks like the main affect of
setting write permissions is that the page can be marked as TLB_NOTDIRTY.
I don't see any other impacts (related to the dirty bit) for giving a
page write permissions.
Setting write permission on dirty PTEs results in userspace inside a
Hypervisor guest (VU) becoming corrupted. This appears to be because it
ends up with write permission in the second stage translation in cases
where we aren't doing a store.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
---
target/riscv/cpu_helper.c | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index d3ba9efb02..e2da2a4787 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -572,10 +572,8 @@ restart:
if ((pte & PTE_X)) {
*prot |= PAGE_EXEC;
}
- /* add write permission on stores or if the page is already dirty,
- so that we TLB miss on later writes to update the dirty bit */
- if ((pte & PTE_W) &&
- (access_type == MMU_DATA_STORE || (pte & PTE_D))) {
+ /* add write permission on stores */
+ if ((pte & PTE_W) && (access_type == MMU_DATA_STORE)) {
*prot |= PAGE_WRITE;
}
return TRANSLATE_SUCCESS;
--
2.26.1.301.g55bc3eb7cb9-goog
^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [PULL 1/6] target/riscv: Don't set write permissions on dirty PTEs
2020-04-21 19:09 ` [PULL 1/6] target/riscv: Don't set write permissions on dirty PTEs Palmer Dabbelt
@ 2020-04-21 19:20 ` Alistair Francis
0 siblings, 0 replies; 10+ messages in thread
From: Alistair Francis @ 2020-04-21 19:20 UTC (permalink / raw)
To: Palmer Dabbelt
Cc: Peter Maydell, Alistair Francis, Bin Meng, open list:RISC-V,
qemu-devel@nongnu.org Developers
On Tue, Apr 21, 2020 at 12:19 PM Palmer Dabbelt
<palmerdabbelt@google.com> wrote:
>
> From: Alistair Francis <alistair.francis@wdc.com>
>
> The RISC-V spec specifies that when a write happens and the D bit is
> clear the implementation will set the bit in the PTE. It does not
> describe that the PTE being dirty means that we should provide write
> access. This patch removes the write access granted to pages when the
> dirty bit is set.
>
> Following the prot variable we can see that it affects all of these
> functions:
> riscv_cpu_tlb_fill()
> tlb_set_page()
> tlb_set_page_with_attrs()
> address_space_translate_for_iotlb()
>
> Looking at the cputlb code (tlb_set_page_with_attrs() and
> address_space_translate_for_iotlb()) it looks like the main affect of
> setting write permissions is that the page can be marked as TLB_NOTDIRTY.
>
> I don't see any other impacts (related to the dirty bit) for giving a
> page write permissions.
>
> Setting write permission on dirty PTEs results in userspace inside a
> Hypervisor guest (VU) becoming corrupted. This appears to be because it
> ends up with write permission in the second stage translation in cases
> where we aren't doing a store.
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
This commit is wrong. Please do not apply this.
Alistair
> ---
> target/riscv/cpu_helper.c | 6 ++----
> 1 file changed, 2 insertions(+), 4 deletions(-)
>
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index d3ba9efb02..e2da2a4787 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -572,10 +572,8 @@ restart:
> if ((pte & PTE_X)) {
> *prot |= PAGE_EXEC;
> }
> - /* add write permission on stores or if the page is already dirty,
> - so that we TLB miss on later writes to update the dirty bit */
> - if ((pte & PTE_W) &&
> - (access_type == MMU_DATA_STORE || (pte & PTE_D))) {
> + /* add write permission on stores */
> + if ((pte & PTE_W) && (access_type == MMU_DATA_STORE)) {
> *prot |= PAGE_WRITE;
> }
> return TRANSLATE_SUCCESS;
> --
> 2.26.1.301.g55bc3eb7cb9-goog
>
>
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PULL 2/6] riscv: Don't use stage-2 PTE lookup protection flags
2020-04-21 19:09 [PULL] RISC-V Patches for 5.0-rc4 Palmer Dabbelt
2020-04-21 19:09 ` [PULL 1/6] target/riscv: Don't set write permissions on dirty PTEs Palmer Dabbelt
@ 2020-04-21 19:09 ` Palmer Dabbelt
2020-04-21 19:09 ` [PULL 3/6] riscv: AND stage-1 and stage-2 " Palmer Dabbelt
` (4 subsequent siblings)
6 siblings, 0 replies; 10+ messages in thread
From: Palmer Dabbelt @ 2020-04-21 19:09 UTC (permalink / raw)
To: Peter Maydell
Cc: qemu-riscv, qemu-devel, Alistair Francis, Richard Henderson,
Palmer Dabbelt
From: Alistair Francis <alistair.francis@wdc.com>
When doing the fist of a two stage lookup (Hypervisor extensions) don't
set the current protection flags from the second stage lookup of the
base address PTE.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
---
target/riscv/cpu_helper.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index e2da2a4787..48e112808b 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -452,10 +452,11 @@ restart:
hwaddr pte_addr;
if (two_stage && first_stage) {
+ int vbase_prot;
hwaddr vbase;
/* Do the second stage translation on the base PTE address. */
- get_physical_address(env, &vbase, prot, base, access_type,
+ get_physical_address(env, &vbase, &vbase_prot, base, access_type,
mmu_idx, false, true);
pte_addr = vbase + idx * ptesize;
--
2.26.1.301.g55bc3eb7cb9-goog
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PULL 3/6] riscv: AND stage-1 and stage-2 protection flags
2020-04-21 19:09 [PULL] RISC-V Patches for 5.0-rc4 Palmer Dabbelt
2020-04-21 19:09 ` [PULL 1/6] target/riscv: Don't set write permissions on dirty PTEs Palmer Dabbelt
2020-04-21 19:09 ` [PULL 2/6] riscv: Don't use stage-2 PTE lookup protection flags Palmer Dabbelt
@ 2020-04-21 19:09 ` Palmer Dabbelt
2020-04-21 19:09 ` [PULL 4/6] riscv/sifive_u: Fix up file ordering Palmer Dabbelt
` (3 subsequent siblings)
6 siblings, 0 replies; 10+ messages in thread
From: Palmer Dabbelt @ 2020-04-21 19:09 UTC (permalink / raw)
To: Peter Maydell
Cc: qemu-riscv, qemu-devel, Alistair Francis, Richard Henderson,
Palmer Dabbelt
From: Alistair Francis <alistair.francis@wdc.com>
Take the result of stage-1 and stage-2 page table walks and AND the two
protection flags together. This way we require both to set permissions
instead of just stage-2.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
---
target/riscv/cpu_helper.c | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 48e112808b..700ef052b0 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -705,7 +705,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
#ifndef CONFIG_USER_ONLY
vaddr im_address;
hwaddr pa = 0;
- int prot;
+ int prot, prot2;
bool pmp_violation = false;
bool m_mode_two_stage = false;
bool hs_mode_two_stage = false;
@@ -755,13 +755,15 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
/* Second stage lookup */
im_address = pa;
- ret = get_physical_address(env, &pa, &prot, im_address,
+ ret = get_physical_address(env, &pa, &prot2, im_address,
access_type, mmu_idx, false, true);
qemu_log_mask(CPU_LOG_MMU,
"%s 2nd-stage address=%" VADDR_PRIx " ret %d physical "
TARGET_FMT_plx " prot %d\n",
- __func__, im_address, ret, pa, prot);
+ __func__, im_address, ret, pa, prot2);
+
+ prot &= prot2;
if (riscv_feature(env, RISCV_FEATURE_PMP) &&
(ret == TRANSLATE_SUCCESS) &&
--
2.26.1.301.g55bc3eb7cb9-goog
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PULL 4/6] riscv/sifive_u: Fix up file ordering
2020-04-21 19:09 [PULL] RISC-V Patches for 5.0-rc4 Palmer Dabbelt
` (2 preceding siblings ...)
2020-04-21 19:09 ` [PULL 3/6] riscv: AND stage-1 and stage-2 " Palmer Dabbelt
@ 2020-04-21 19:09 ` Palmer Dabbelt
2020-04-21 19:10 ` [PULL 5/6] riscv/sifive_u: Add a serial property to the sifive_u SoC Palmer Dabbelt
` (2 subsequent siblings)
6 siblings, 0 replies; 10+ messages in thread
From: Palmer Dabbelt @ 2020-04-21 19:09 UTC (permalink / raw)
To: Peter Maydell
Cc: qemu-riscv, qemu-devel, Alistair Francis, Bin Meng,
Palmer Dabbelt
From: Alistair Francis <alistair.francis@wdc.com>
Split the file into clear machine and SoC sections.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
---
hw/riscv/sifive_u.c | 109 ++++++++++++++++++++++----------------------
1 file changed, 55 insertions(+), 54 deletions(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 56351c4faa..d0ea6803db 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -312,7 +312,7 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
g_free(nodename);
}
-static void riscv_sifive_u_init(MachineState *machine)
+static void sifive_u_machine_init(MachineState *machine)
{
const struct MemmapEntry *memmap = sifive_u_memmap;
SiFiveUState *s = RISCV_U_MACHINE(machine);
@@ -403,6 +403,60 @@ static void riscv_sifive_u_init(MachineState *machine)
&address_space_memory);
}
+static bool sifive_u_machine_get_start_in_flash(Object *obj, Error **errp)
+{
+ SiFiveUState *s = RISCV_U_MACHINE(obj);
+
+ return s->start_in_flash;
+}
+
+static void sifive_u_machine_set_start_in_flash(Object *obj, bool value, Error **errp)
+{
+ SiFiveUState *s = RISCV_U_MACHINE(obj);
+
+ s->start_in_flash = value;
+}
+
+static void sifive_u_machine_instance_init(Object *obj)
+{
+ SiFiveUState *s = RISCV_U_MACHINE(obj);
+
+ s->start_in_flash = false;
+ object_property_add_bool(obj, "start-in-flash", sifive_u_machine_get_start_in_flash,
+ sifive_u_machine_set_start_in_flash, NULL);
+ object_property_set_description(obj, "start-in-flash",
+ "Set on to tell QEMU's ROM to jump to " \
+ "flash. Otherwise QEMU will jump to DRAM",
+ NULL);
+}
+
+
+static void sifive_u_machine_class_init(ObjectClass *oc, void *data)
+{
+ MachineClass *mc = MACHINE_CLASS(oc);
+
+ mc->desc = "RISC-V Board compatible with SiFive U SDK";
+ mc->init = sifive_u_machine_init;
+ mc->max_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + SIFIVE_U_COMPUTE_CPU_COUNT;
+ mc->min_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + 1;
+ mc->default_cpus = mc->min_cpus;
+}
+
+static const TypeInfo sifive_u_machine_typeinfo = {
+ .name = MACHINE_TYPE_NAME("sifive_u"),
+ .parent = TYPE_MACHINE,
+ .class_init = sifive_u_machine_class_init,
+ .instance_init = sifive_u_machine_instance_init,
+ .instance_size = sizeof(SiFiveUState),
+};
+
+static void sifive_u_machine_init_register_types(void)
+{
+ type_register_static(&sifive_u_machine_typeinfo);
+}
+
+type_init(sifive_u_machine_init_register_types)
+
static void riscv_sifive_u_soc_init(Object *obj)
{
MachineState *ms = MACHINE(qdev_get_machine());
@@ -443,33 +497,6 @@ static void riscv_sifive_u_soc_init(Object *obj)
TYPE_CADENCE_GEM);
}
-static bool sifive_u_get_start_in_flash(Object *obj, Error **errp)
-{
- SiFiveUState *s = RISCV_U_MACHINE(obj);
-
- return s->start_in_flash;
-}
-
-static void sifive_u_set_start_in_flash(Object *obj, bool value, Error **errp)
-{
- SiFiveUState *s = RISCV_U_MACHINE(obj);
-
- s->start_in_flash = value;
-}
-
-static void riscv_sifive_u_machine_instance_init(Object *obj)
-{
- SiFiveUState *s = RISCV_U_MACHINE(obj);
-
- s->start_in_flash = false;
- object_property_add_bool(obj, "start-in-flash", sifive_u_get_start_in_flash,
- sifive_u_set_start_in_flash, NULL);
- object_property_set_description(obj, "start-in-flash",
- "Set on to tell QEMU's ROM to jump to " \
- "flash. Otherwise QEMU will jump to DRAM",
- NULL);
-}
-
static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp)
{
MachineState *ms = MACHINE(qdev_get_machine());
@@ -607,29 +634,3 @@ static void riscv_sifive_u_soc_register_types(void)
}
type_init(riscv_sifive_u_soc_register_types)
-
-static void riscv_sifive_u_machine_class_init(ObjectClass *oc, void *data)
-{
- MachineClass *mc = MACHINE_CLASS(oc);
-
- mc->desc = "RISC-V Board compatible with SiFive U SDK";
- mc->init = riscv_sifive_u_init;
- mc->max_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + SIFIVE_U_COMPUTE_CPU_COUNT;
- mc->min_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + 1;
- mc->default_cpus = mc->min_cpus;
-}
-
-static const TypeInfo riscv_sifive_u_machine_typeinfo = {
- .name = MACHINE_TYPE_NAME("sifive_u"),
- .parent = TYPE_MACHINE,
- .class_init = riscv_sifive_u_machine_class_init,
- .instance_init = riscv_sifive_u_machine_instance_init,
- .instance_size = sizeof(SiFiveUState),
-};
-
-static void riscv_sifive_u_machine_init_register_types(void)
-{
- type_register_static(&riscv_sifive_u_machine_typeinfo);
-}
-
-type_init(riscv_sifive_u_machine_init_register_types)
--
2.26.1.301.g55bc3eb7cb9-goog
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PULL 5/6] riscv/sifive_u: Add a serial property to the sifive_u SoC
2020-04-21 19:09 [PULL] RISC-V Patches for 5.0-rc4 Palmer Dabbelt
` (3 preceding siblings ...)
2020-04-21 19:09 ` [PULL 4/6] riscv/sifive_u: Fix up file ordering Palmer Dabbelt
@ 2020-04-21 19:10 ` Palmer Dabbelt
2020-04-21 19:10 ` [PULL 6/6] riscv/sifive_u: Add a serial property to the sifive_u machine Palmer Dabbelt
2020-04-21 19:27 ` [PULL] RISC-V Patches for 5.0-rc4 Peter Maydell
6 siblings, 0 replies; 10+ messages in thread
From: Palmer Dabbelt @ 2020-04-21 19:10 UTC (permalink / raw)
To: Peter Maydell
Cc: qemu-riscv, qemu-devel, Alistair Francis, Bin Meng,
Palmer Dabbelt
From: Alistair Francis <alistair.francis@wdc.com>
At present the board serial number is hard-coded to 1, and passed
to OTP model during initialization. Firmware (FSBL, U-Boot) uses
the serial number to generate a unique MAC address for the on-chip
ethernet controller. When multiple QEMU 'sifive_u' instances are
created and connected to the same subnet, they all have the same
MAC address hence it creates a unusable network.
A new "serial" property is introduced to the sifive_u SoC to specify
the board serial number. When not given, the default serial number
1 is used.
Suggested-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
---
hw/riscv/sifive_u.c | 8 +++++++-
include/hw/riscv/sifive_u.h | 2 ++
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index d0ea6803db..9bfd16d2bb 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -492,7 +492,6 @@ static void riscv_sifive_u_soc_init(Object *obj)
TYPE_SIFIVE_U_PRCI);
sysbus_init_child_obj(obj, "otp", &s->otp, sizeof(s->otp),
TYPE_SIFIVE_U_OTP);
- qdev_prop_set_uint32(DEVICE(&s->otp), "serial", OTP_SERIAL);
sysbus_init_child_obj(obj, "gem", &s->gem, sizeof(s->gem),
TYPE_CADENCE_GEM);
}
@@ -585,6 +584,7 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp)
object_property_set_bool(OBJECT(&s->prci), true, "realized", &err);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->prci), 0, memmap[SIFIVE_U_PRCI].base);
+ qdev_prop_set_uint32(DEVICE(&s->otp), "serial", s->serial);
object_property_set_bool(OBJECT(&s->otp), true, "realized", &err);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->otp), 0, memmap[SIFIVE_U_OTP].base);
@@ -611,10 +611,16 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp)
memmap[SIFIVE_U_GEM_MGMT].base, memmap[SIFIVE_U_GEM_MGMT].size);
}
+static Property riscv_sifive_u_soc_props[] = {
+ DEFINE_PROP_UINT32("serial", SiFiveUSoCState, serial, OTP_SERIAL),
+ DEFINE_PROP_END_OF_LIST()
+};
+
static void riscv_sifive_u_soc_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
+ device_class_set_props(dc, riscv_sifive_u_soc_props);
dc->realize = riscv_sifive_u_soc_realize;
/* Reason: Uses serial_hds in realize function, thus can't be used twice */
dc->user_creatable = false;
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index 82667b5746..a2baa1de5f 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -42,6 +42,8 @@ typedef struct SiFiveUSoCState {
SiFiveUPRCIState prci;
SiFiveUOTPState otp;
CadenceGEMState gem;
+
+ uint32_t serial;
} SiFiveUSoCState;
#define TYPE_RISCV_U_MACHINE MACHINE_TYPE_NAME("sifive_u")
--
2.26.1.301.g55bc3eb7cb9-goog
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PULL 6/6] riscv/sifive_u: Add a serial property to the sifive_u machine
2020-04-21 19:09 [PULL] RISC-V Patches for 5.0-rc4 Palmer Dabbelt
` (4 preceding siblings ...)
2020-04-21 19:10 ` [PULL 5/6] riscv/sifive_u: Add a serial property to the sifive_u SoC Palmer Dabbelt
@ 2020-04-21 19:10 ` Palmer Dabbelt
2020-04-21 19:27 ` [PULL] RISC-V Patches for 5.0-rc4 Peter Maydell
6 siblings, 0 replies; 10+ messages in thread
From: Palmer Dabbelt @ 2020-04-21 19:10 UTC (permalink / raw)
To: Peter Maydell
Cc: qemu-riscv, qemu-devel, Bin Meng, Palmer Dabbelt,
Alistair Francis
From: Bin Meng <bmeng.cn@gmail.com>
At present the board serial number is hard-coded to 1, and passed
to OTP model during initialization. Firmware (FSBL, U-Boot) uses
the serial number to generate a unique MAC address for the on-chip
ethernet controller. When multiple QEMU 'sifive_u' instances are
created and connected to the same subnet, they all have the same
MAC address hence it creates a unusable network.
A new "serial" property is introduced to specify the board serial
number. When not given, the default serial number 1 is used.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1573916930-19068-1-git-send-email-bmeng.cn@gmail.com>
[ Changed by AF:
- Use the SoC's serial property to pass the info to the SoC
- Fixup commit title
- Rebase on file restructuring
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
---
hw/riscv/sifive_u.c | 20 ++++++++++++++++++++
include/hw/riscv/sifive_u.h | 1 +
2 files changed, 21 insertions(+)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 9bfd16d2bb..eb0abcae89 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -34,6 +34,7 @@
#include "qemu/log.h"
#include "qemu/error-report.h"
#include "qapi/error.h"
+#include "qapi/visitor.h"
#include "hw/boards.h"
#include "hw/loader.h"
#include "hw/sysbus.h"
@@ -326,6 +327,8 @@ static void sifive_u_machine_init(MachineState *machine)
object_initialize_child(OBJECT(machine), "soc", &s->soc,
sizeof(s->soc), TYPE_RISCV_U_SOC,
&error_abort, NULL);
+ object_property_set_uint(OBJECT(&s->soc), s->serial, "serial",
+ &error_abort);
object_property_set_bool(OBJECT(&s->soc), true, "realized",
&error_abort);
@@ -417,6 +420,18 @@ static void sifive_u_machine_set_start_in_flash(Object *obj, bool value, Error *
s->start_in_flash = value;
}
+static void sifive_u_machine_get_serial(Object *obj, Visitor *v, const char *name,
+ void *opaque, Error **errp)
+{
+ visit_type_uint32(v, name, (uint32_t *)opaque, errp);
+}
+
+static void sifive_u_machine_set_serial(Object *obj, Visitor *v, const char *name,
+ void *opaque, Error **errp)
+{
+ visit_type_uint32(v, name, (uint32_t *)opaque, errp);
+}
+
static void sifive_u_machine_instance_init(Object *obj)
{
SiFiveUState *s = RISCV_U_MACHINE(obj);
@@ -428,6 +443,11 @@ static void sifive_u_machine_instance_init(Object *obj)
"Set on to tell QEMU's ROM to jump to " \
"flash. Otherwise QEMU will jump to DRAM",
NULL);
+
+ s->serial = OTP_SERIAL;
+ object_property_add(obj, "serial", "uint32", sifive_u_machine_get_serial,
+ sifive_u_machine_set_serial, NULL, &s->serial, NULL);
+ object_property_set_description(obj, "serial", "Board serial number", NULL);
}
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index a2baa1de5f..16c297ec5f 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -61,6 +61,7 @@ typedef struct SiFiveUState {
int fdt_size;
bool start_in_flash;
+ uint32_t serial;
} SiFiveUState;
enum {
--
2.26.1.301.g55bc3eb7cb9-goog
^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [PULL] RISC-V Patches for 5.0-rc4
2020-04-21 19:09 [PULL] RISC-V Patches for 5.0-rc4 Palmer Dabbelt
` (5 preceding siblings ...)
2020-04-21 19:10 ` [PULL 6/6] riscv/sifive_u: Add a serial property to the sifive_u machine Palmer Dabbelt
@ 2020-04-21 19:27 ` Peter Maydell
2020-04-21 19:32 ` Palmer Dabbelt
6 siblings, 1 reply; 10+ messages in thread
From: Peter Maydell @ 2020-04-21 19:27 UTC (permalink / raw)
To: Palmer Dabbelt; +Cc: Alistair Francis, open list:RISC-V, QEMU Developers
On Tue, 21 Apr 2020 at 20:19, Palmer Dabbelt <palmerdabbelt@google.com> wrote:
> ----------------------------------------------------------------
> RISC-V Patches for 5.0-rc4
>
> This contains handful of patches that I'd like to target for 5.0. I know it's
> a bit late, I thought I'd already sent these out but must have managed to miss
> doing so. The patches include:
>
> * A handful of fixes to PTE lookups related to H-mode support.
> * The addition of a serial number fo the SiFive U implementetaion, which allows
> bootloaders to generate a sane MAC address.
>
> These pass "make check" and boot Linux for me.
>
> ----------------------------------------------------------------
> Peter: Sorry I dropped the ball here. I can understand if it's too late for
> 5.0, but if there's still going to be an rc4 then I'd love to have these
> included.
> ----------------------------------------------------------------
Nope, sorry. rc4 has technically not been tagged yet, but especially
the serial-property stuff is too big a code change at this point
(it includes one "let's just refactor and rearrange some code"
patch which is really not rc4 material.)
Also these patches have been on the list for over a month -- if
they were 5.0-worthy there's been plenty of time for them to be
put in.
Plus the last email from Alistair on the "target/riscv: Don't set
write permissions on dirty PTEs" patch thread is a note saying
it shouldn't be applied, unless I've got confused.
thanks
-- PMM
^ permalink raw reply [flat|nested] 10+ messages in thread* Re: [PULL] RISC-V Patches for 5.0-rc4
2020-04-21 19:27 ` [PULL] RISC-V Patches for 5.0-rc4 Peter Maydell
@ 2020-04-21 19:32 ` Palmer Dabbelt
0 siblings, 0 replies; 10+ messages in thread
From: Palmer Dabbelt @ 2020-04-21 19:32 UTC (permalink / raw)
To: Peter Maydell; +Cc: Alistair Francis, qemu-riscv, qemu-devel
On Tue, 21 Apr 2020 12:27:50 PDT (-0700), Peter Maydell wrote:
> On Tue, 21 Apr 2020 at 20:19, Palmer Dabbelt <palmerdabbelt@google.com> wrote:
>> ----------------------------------------------------------------
>> RISC-V Patches for 5.0-rc4
>>
>> This contains handful of patches that I'd like to target for 5.0. I know it's
>> a bit late, I thought I'd already sent these out but must have managed to miss
>> doing so. The patches include:
>>
>> * A handful of fixes to PTE lookups related to H-mode support.
>> * The addition of a serial number fo the SiFive U implementetaion, which allows
>> bootloaders to generate a sane MAC address.
>>
>> These pass "make check" and boot Linux for me.
>>
>> ----------------------------------------------------------------
>> Peter: Sorry I dropped the ball here. I can understand if it's too late for
>> 5.0, but if there's still going to be an rc4 then I'd love to have these
>> included.
>> ----------------------------------------------------------------
>
> Nope, sorry. rc4 has technically not been tagged yet, but especially
> the serial-property stuff is too big a code change at this point
> (it includes one "let's just refactor and rearrange some code"
> patch which is really not rc4 material.)
> Also these patches have been on the list for over a month -- if
> they were 5.0-worthy there's been plenty of time for them to be
> put in.
>
> Plus the last email from Alistair on the "target/riscv: Don't set
> write permissions on dirty PTEs" patch thread is a note saying
> it shouldn't be applied, unless I've got confused.
OK, no problem.
>
> thanks
> -- PMM
^ permalink raw reply [flat|nested] 10+ messages in thread