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From: Peter Maydell <peter.maydell@linaro.org>
Date: Sat, 18 Aug 2018 11:05:46 +0100
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Subject: Re: [Qemu-devel] [Qemu-arm] [PATCH 08/16] hw/misc/iotkit-secctl:
 Wire up registers for controlling MSCs
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To: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= <f4bug@amsat.org>
Cc: qemu-arm <qemu-arm@nongnu.org>, QEMU Developers <qemu-devel@nongnu.org>, "patches@linaro.org" <patches@linaro.org>

On 18 August 2018 at 01:37, Philippe Mathieu-Daud=C3=A9 <f4bug@amsat.org> w=
rote:
> On 08/09/2018 10:01 AM, Peter Maydell wrote:
>> The IoTKit does not have any Master Security Contollers itself,
>> but it does provide registers in the secure privilege control
>> block which allow control of MSCs in the external system.
>> Add support for these registers.
>>
>> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
>> ---

>>      case A_SECMSCINTEN:
>> -        qemu_log_mask(LOG_UNIMP,
>> -                      "IoTKit SecCtl S block write: "
>> -                      "unimplemented offset 0x%x\n", offset);
>
> Maybe:
>
>            if (value & ~0xffff) {
>                GUEST_ERROR(...)
>            }

We don't generally bother to log writes of raz bits as errors.


thanks
-- PMM