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From: Peter Maydell <peter.maydell@linaro.org>
To: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Cc: blauwirbel@gmail.com, edgar.iglesias@gmail.com,
	kraxel@redhat.com, qemu-devel@nongnu.org, mst@redhat.com
Subject: Re: [Qemu-devel] [PATCH v2 2/5] register: Add Register API
Date: Fri, 5 Apr 2013 10:26:33 +0100	[thread overview]
Message-ID: <CAFEAcA9aSytRUn-4Ab9XsfanFF0cjjkAuoR4DeZNJvwRh+PFXA@mail.gmail.com> (raw)
In-Reply-To: <b58f3b5c3be5a78765ae759e926a06a71a03adc0.1365151096.git.peter.crosthwaite@xilinx.com>

On 5 April 2013 09:43, Peter Crosthwaite <peter.crosthwaite@xilinx.com> wrote:
> This API provides some encapsulation of registers and factors our some
> common functionality to common code. Bits of device state (usually MMIO
> registers), often have all sorts of access restrictions and semantics
> associated with them. This API allow you to define what those
> restrictions are on a bit-by-bit basis.
> +void register_write(RegisterInfo *reg, uint64_t val, uint64_t we)
> +{
> +    uint64_t old_val, new_val, test;
> +    const RegisterAccessInfo *ac;
> +    const RegisterAccessError *rae;
> +
> +    assert(reg);
> +
> +    ac = reg->access;
> +    if (!ac || !ac->name) {
> +        qemu_log_mask(LOG_GUEST_ERROR, "%s: write to undefined device state "
> +                      "(written value: %#" PRIx64 ")\n", reg->prefix, val);
> +        return;
> +    }
> +
> +    uint32_t no_w0_mask = ac->ro | ac->w1c | ac->nw0 | ~we;
> +    uint32_t no_w1_mask = ac->ro | ac->w1c | ac->nw1 | ~we;
> +
> +    if (reg->debug) {
> +        fprintf(stderr, "%s:%s: write of value %#" PRIx64 "\n", reg->prefix,
> +                ac->name, val);
> +    }
> +
> +    if (qemu_loglevel_mask(LOG_GUEST_ERROR)) {
> +        for (rae = ac->ge1; rae && rae->mask; rae++) {
> +            test = val & rae->mask;
> +            if (test) {
> +                register_write_log(reg, 1, test, LOG_GUEST_ERROR,
> +                                   "invalid", rae->reason);
> +            }
> +        }
> +        for (rae = ac->ge0; rae && rae->mask; rae++) {
> +            test = val & rae->mask;
> +            if (test) {
> +                register_write_log(reg, 0, test, LOG_GUEST_ERROR,
> +                                   "invalid", rae->reason);
> +            }
> +        }
> +    }
> +
> +    if (qemu_loglevel_mask(LOG_UNIMP)) {
> +        for (rae = ac->ui1; rae && rae->mask; rae++) {
> +            test = val & rae->mask;
> +            if (test) {
> +                register_write_log(reg, 1, test, LOG_GUEST_ERROR,
> +                                   "unimplmented", rae->reason);
> +            }
> +        }
> +        for (rae = ac->ui0; rae && rae->mask; rae++) {
> +            test = val & rae->mask;
> +            if (test) {
> +                register_write_log(reg, 0, test, LOG_GUEST_ERROR,
> +                                   "unimplemented", rae->reason);
> +            }
> +        }
> +    }
> +
> +    assert(reg->data);
> +    old_val = register_read_val(reg);
> +
> +    new_val = val & ~(no_w1_mask & val);
> +    new_val |= no_w1_mask & old_val & val;
> +    new_val |= no_w0_mask & old_val & ~val;
> +    new_val &= ~(val & ac->w1c);
> +
> +    if (ac->pre_write) {
> +        new_val = ac->pre_write(reg, new_val);
> +    }
> +    register_write_val(reg, new_val);
> +    if (ac->post_write) {
> +        ac->post_write(reg, new_val);
> +    }
> +}

Wow, this feels pretty heavyweight for "write a register"...

-- PMM

  reply	other threads:[~2013-04-05  9:27 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-04-05  8:43 [Qemu-devel] [PATCH v2 0/5] Data Driven device registers & Zynq DEVCFG Peter Crosthwaite
2013-04-05  8:43 ` [Qemu-devel] [PATCH v2 1/5] bitops: Add ONES macro Peter Crosthwaite
2013-04-05  8:53   ` Peter Maydell
2013-04-05  9:11     ` Peter Crosthwaite
2013-04-05  9:24       ` Peter Maydell
2013-04-05  8:43 ` [Qemu-devel] [PATCH v2 2/5] register: Add Register API Peter Crosthwaite
2013-04-05  9:26   ` Peter Maydell [this message]
2013-04-05  9:49     ` Peter Crosthwaite
2013-04-07 22:40       ` Peter Crosthwaite
2013-04-15  7:11         ` Gerd Hoffmann
2013-04-05  8:43 ` [Qemu-devel] [PATCH v2 3/5] register: Add Memory API glue Peter Crosthwaite
2013-04-05 10:07   ` Paolo Bonzini
2013-04-05  8:43 ` [Qemu-devel] [PATCH v2 4/5] xilinx_devcfg: Zynq devcfg device model Peter Crosthwaite
2013-04-05  8:43 ` [Qemu-devel] [PATCH v2 5/5] xilinx_zynq: added devcfg to machine model Peter Crosthwaite

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