From: Peter Maydell <peter.maydell@linaro.org>
To: Laurent Vivier <laurent@vivier.eu>
Cc: QEMU Developers <qemu-devel@nongnu.org>,
Andreas Schwab <schwab@linux-m68k.org>,
Aurelien Jarno <aurelien@aurel32.net>,
Richard Henderson <rth@twiddle.net>
Subject: Re: [Qemu-devel] [PATCH v3 02/16] softloat: disable floatx80_invalid_encoding() for m68k
Date: Wed, 8 Feb 2017 22:58:00 +0000 [thread overview]
Message-ID: <CAFEAcA9dRrmY+86t6uzqnaRynvV4AW3vcCfaqRJKT1gt=E_OJg@mail.gmail.com> (raw)
In-Reply-To: <20170207005930.28327-3-laurent@vivier.eu>
On 7 February 2017 at 00:59, Laurent Vivier <laurent@vivier.eu> wrote:
> According to the comment, this definition of invalid encoding is given
> by intel developer's manual, and doesn't work with the behavior
> of 680x0 FPU.
>
> CC: Andreas Schwab <schwab@linux-m68k.org>
> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
> ---
> fpu/softfloat.c | 31 +++++++++++++++++++++++++++++++
> include/fpu/softfloat.h | 15 ---------------
> 2 files changed, 31 insertions(+), 15 deletions(-)
>
> diff --git a/fpu/softfloat.c b/fpu/softfloat.c
> index c295f31..f95b19f 100644
> --- a/fpu/softfloat.c
> +++ b/fpu/softfloat.c
> @@ -4799,6 +4799,37 @@ int float64_unordered_quiet(float64 a, float64 b, float_status *status)
> }
>
> /*----------------------------------------------------------------------------
> +| Return whether the given value is an invalid floatx80 encoding.
> +| Invalid floatx80 encodings arise when the integer bit is not set, but
> +| the exponent is not zero. The only times the integer bit is permitted to
> +| be zero is in subnormal numbers and the value zero.
> +| This includes what the Intel software developer's manual calls pseudo-NaNs,
> +| pseudo-infinities and un-normal numbers. It does not include
> +| pseudo-denormals, which must still be correctly handled as inputs even
> +| if they are never generated as outputs.
> +*----------------------------------------------------------------------------*/
> +static inline bool floatx80_invalid_encoding(floatx80 a)
> +{
> +#if defined(TARGET_M68K)
> + /*-------------------------------------------------------------------------
> + | M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
> + | 1.6.2 Denormalized Numbers
> + | Since the extended-precision data format has an explicit integer bit,
> + | a number can be formatted with a nonzero exponent, less than the maximum
> + | value, and a zero integer bit. The IEEE 754 standard does not define a
> + | zero integer bit. Such a number is an unnormalized number. Hardware does
> + | not directly support denormalized and unnormalized numbers, but
> + | implicitly supports them by trapping them as unimplemented data types,
> + | allowing efficient conversion in software.
> + *------------------------------------------------------------------------*/
This comment says that numbers of the form that this function
identifies (zero integer bit and nonzero exponent) are
supposed to trap on m68k. That suggests that the target/m68k code
is going to need to catch this case before it calls softfloat
code. So (a) we don't care what the softfloat code does
with these representations because they'll never get to it
and (b) the m68k code could probably use floatx80_invalid_encoding()
as a function to identify where it needs to trap, which it
can't do if it's moved out of softfloat.h.
Either way this change doesn't seem right given what the
comment describes...
thanks
-- PMM
next prev parent reply other threads:[~2017-02-08 22:58 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-02-07 0:59 [Qemu-devel] [PATCH v3 00/16] target-m68k: implement 680x0 FPU Laurent Vivier
2017-02-07 0:59 ` [Qemu-devel] [PATCH v3 01/16] softfloat: define 680x0 specific values Laurent Vivier
2017-02-08 21:30 ` Richard Henderson
2017-02-07 0:59 ` [Qemu-devel] [PATCH v3 02/16] softloat: disable floatx80_invalid_encoding() for m68k Laurent Vivier
2017-02-08 21:32 ` Richard Henderson
2017-02-08 22:58 ` Peter Maydell [this message]
2017-02-09 8:07 ` Laurent Vivier
2017-02-07 0:59 ` [Qemu-devel] [PATCH v3 03/16] target-m68k: move FPU helpers to fpu_helper.c Laurent Vivier
2017-02-08 21:33 ` Richard Henderson
2017-02-07 0:59 ` [Qemu-devel] [PATCH v3 04/16] target-m68k: define ext_opsize Laurent Vivier
2017-02-08 21:33 ` Richard Henderson
2017-02-07 0:59 ` [Qemu-devel] [PATCH v3 05/16] target-m68k: use floatx80 internally Laurent Vivier
2017-02-15 22:59 ` Richard Henderson
2017-02-07 0:59 ` [Qemu-devel] [PATCH v3 06/16] target-m68k: add FPCR and FPSR Laurent Vivier
2017-02-16 1:10 ` Richard Henderson
2017-02-07 0:59 ` [Qemu-devel] [PATCH v3 07/16] target-m68k: manage FPU exceptions Laurent Vivier
2017-02-16 1:16 ` Richard Henderson
2017-02-07 0:59 ` [Qemu-devel] [PATCH v3 08/16] target-m68k: define 96bit FP registers for gdb on 680x0 Laurent Vivier
2017-02-16 1:17 ` Richard Henderson
2017-02-07 0:59 ` [Qemu-devel] [PATCH v3 09/16] target-m68k: add fmovem Laurent Vivier
2017-02-16 1:22 ` Richard Henderson
2017-02-07 0:59 ` [Qemu-devel] [PATCH v3 10/16] target-m68k: add fscc Laurent Vivier
2017-02-16 1:27 ` Richard Henderson
2017-02-07 0:59 ` [Qemu-devel] [PATCH v3 11/16] target-m68k: add fmovecr Laurent Vivier
2017-02-16 1:28 ` Richard Henderson
2017-02-07 0:59 ` [Qemu-devel] [PATCH v3 12/16] target-m68k: add fscale, fgetman, fgetexp and fmod Laurent Vivier
2017-02-16 1:34 ` Richard Henderson
2017-02-07 0:59 ` [Qemu-devel] [PATCH v3 13/16] target-m68k: add fsglmul and fsgldiv Laurent Vivier
2017-02-16 1:36 ` Richard Henderson
2017-02-07 0:59 ` [Qemu-devel] [PATCH v3 14/16] target-m68k: add explicit single and double precision operations Laurent Vivier
2017-02-16 1:41 ` Richard Henderson
2017-02-07 0:59 ` [Qemu-devel] [PATCH v3 15/16] target-m68k: add more FPU instructions Laurent Vivier
2017-02-16 1:46 ` Richard Henderson
2017-02-16 10:18 ` Andreas Schwab
2017-02-16 21:01 ` Richard Henderson
2017-02-17 9:06 ` Andreas Schwab
2017-02-07 0:59 ` [Qemu-devel] [PATCH v3 16/16] target-m68k: add fsincos Laurent Vivier
2017-02-07 1:25 ` [Qemu-devel] [PATCH v3 00/16] target-m68k: implement 680x0 FPU no-reply
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