From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56641) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WmkOw-0000p1-3Q for qemu-devel@nongnu.org; Tue, 20 May 2014 09:48:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WmkOp-0002WX-KK for qemu-devel@nongnu.org; Tue, 20 May 2014 09:48:18 -0400 Received: from mail-lb0-f171.google.com ([209.85.217.171]:57980) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WmkOp-0002W2-Dz for qemu-devel@nongnu.org; Tue, 20 May 2014 09:48:11 -0400 Received: by mail-lb0-f171.google.com with SMTP id 10so415474lbg.2 for ; Tue, 20 May 2014 06:48:09 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: <20140520132846.GJ18802@zapo.iiNet> References: <1400491383-6725-1-git-send-email-edgar.iglesias@gmail.com> <1400491383-6725-23-git-send-email-edgar.iglesias@gmail.com> <20140520132846.GJ18802@zapo.iiNet> From: Peter Maydell Date: Tue, 20 May 2014 14:47:49 +0100 Message-ID: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH v3 22/22] RFC: target-arm: Use a 1:1 mapping between EL and MMU index List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: "Edgar E. Iglesias" Cc: "rob.herring@linaro.org" , "peter.crosthwaite@xilinx.com" , Aggeler Fabian , "qemu-devel@nongnu.org" , "agraf@suse.de" , "john.williams@xilinx.com" , "alex.bennee@linaro.org" , "christoffer.dall@linaro.org" , "rth@twiddle.net" On 20 May 2014 14:28, Edgar E. Iglesias wrote: > On Tue, May 20, 2014 at 09:47:47AM +0000, Aggeler Fabian wrote: >> I guess this makes sense. Shouldn=E2=80=99t we implement two more MMUs t= o separate S-EL0/EL0 and S-EL1/EL1 >> at least for ARMv8 with EL3 running in Aarch64 state? > > Maybe with future patches. My understanding is that on aarch64 the world > switch between S/NS requires EL3 firmware to reprogram the TTBR regs. > Currently in QEMU, the re-programming of TTBR will flush the TLBs. We wou= ld > need to do something about that before adding MMU tables for aarch64 Secu= re > EL0/1 does any good. I think it's better to keep it simple for now and le= ave > this as a possible future optimization. > > Another possible future optimization is to add some kind of dynamic alloc= ation > of a limited set of MMU tables for different ASIDs and VMIDs. For emulate= d > virtualization, it might help quite a bit. I think the right way to do that is to have QEMU's TLB structure include some sort of general equivalent to the ASID/VMID mechanism (presumably other target CPUs have some equivalent). Then we can honour 'flush by ASID' as well. (We make a forlorn gesture in this direction with the completely ignored 'flush_global' parameter to tlb_flush().) This is all definitely 'maybe future' stuff though.) thanks -- PMM