From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45827) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XtMs0-0004Ei-ET for Qemu-devel@nongnu.org; Tue, 25 Nov 2014 15:38:01 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XtMrv-0004Zi-4a for Qemu-devel@nongnu.org; Tue, 25 Nov 2014 15:37:56 -0500 Received: from mail-la0-f47.google.com ([209.85.215.47]:36274) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XtMru-0004ZX-TU for Qemu-devel@nongnu.org; Tue, 25 Nov 2014 15:37:51 -0500 Received: by mail-la0-f47.google.com with SMTP id hz20so1279673lab.6 for ; Tue, 25 Nov 2014 12:37:50 -0800 (PST) MIME-Version: 1.0 In-Reply-To: <98093680-8E5F-4290-8008-94FC276CC421@livius.net> References: <98093680-8E5F-4290-8008-94FC276CC421@livius.net> From: Peter Maydell Date: Tue, 25 Nov 2014 20:37:29 +0000 Message-ID: Content-Type: text/plain; charset=UTF-8 Subject: Re: [Qemu-devel] Cortex-M development progress List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Liviu Ionescu Cc: QEMU Developers On 25 November 2014 at 19:58, Liviu Ionescu wrote: > As mentioned in a previous message, I started work on a more detailed implementation for the M profile. > > At first I defined in target-arm/cpu.c the cpu-s for all variants (M0/M0+/M1/M3/M4/M7). > > /* Cortex-M cores. Currently only M3 is tested and fully functional. */ > { .name = "cortex-m0", .initfn = cortex_m0_initfn, > .class_init = arm_v6m_class_init }, > { .name = "cortex-m0p", .initfn = cortex_m0p_initfn, > .class_init = arm_v6m_class_init }, > { .name = "cortex-m1", .initfn = cortex_m1_initfn, > .class_init = arm_v6m_class_init }, > { .name = "cortex-m3", .initfn = cortex_m3_initfn, > .class_init = arm_v7m_class_init }, > { .name = "cortex-m4", .initfn = cortex_m4_initfn, > .class_init = arm_v7m_class_init }, > { .name = "cortex-m7", .initfn = cortex_m7_initfn, > .class_init = arm_v7m_class_init }, > > The proper flags might still need adjustments, but at least we have a starting point. I would recommend concentrating on one of these and getting it right, rather than defining five new cores and dozens of MCUs none of which are actually implemented to their specifications. > According to my tests, the core initialisations are enough > to run a simple SysTick timer application. This just means that code that doesn't really care what CPU it runs on will run on a CPU that claims to be an M0/M4/M7 but is actually more or less an M3. If your code really doesn't care then just run it on our existing Cortex-M3 CPU. Patches which can be integrated into mainline will need to make a reasonable attempt at implementing the actual correct functionality of whichever CPU you pick (either adding the extra features in an M4 or cutting out the features which don't exist in v6M). I'd also strongly prefer not to implement three dozen boards unless we really need them all. Again, start with one and implement a decent subset of the devices it has on it. thanks -- PMM