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From: Peter Maydell <peter.maydell@linaro.org>
To: Richard Henderson <richard.henderson@linaro.org>
Cc: qemu-arm@nongnu.org, Idan Horowitz <idan.horowitz@gmail.com>,
	qemu-devel@nongnu.org
Subject: Re: [PATCH] target/arm: Fix MTE access checks for disabled SEL2
Date: Thu, 31 Mar 2022 09:26:00 +0100	[thread overview]
Message-ID: <CAFEAcA9kTNFeAOUz3BFp+ti=AtZRAk2jQTOjDzLnLANPtM4MdA@mail.gmail.com> (raw)
In-Reply-To: <a2e29af5-705a-19b0-b7ad-0126f8d441b0@linaro.org>

On Mon, 28 Mar 2022 at 19:04, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> On 3/28/22 11:31, Idan Horowitz wrote:
> > While not mentioned anywhere in the actual specification text, the
> > HCR_EL2.ATA bit is treated as '1' when EL2 is disabled at the current
> > security state. This can be observed in the psuedo-code implementation
> > of AArch64.AllocationTagAccessIsEnabled().
> >
> > Signed-off-by: Idan Horowitz <idan.horowitz@gmail.com>
> > ---
> >   target/arm/helper.c    | 2 +-
> >   target/arm/internals.h | 2 +-
> >   2 files changed, 2 insertions(+), 2 deletions(-)
>
> I was immediately thinking, didn't I just fix this?
> But I was patching pauth.  Anyway, good catch.
>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>



Applied to target-arm.next, thanks.

-- PMM


      reply	other threads:[~2022-03-31  8:39 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-03-28 17:31 [PATCH] target/arm: Fix MTE access checks for disabled SEL2 Idan Horowitz
2022-03-28 18:04 ` Richard Henderson
2022-03-31  8:26   ` Peter Maydell [this message]

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