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From: Peter Maydell <peter.maydell@linaro.org>
To: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
Cc: qemu-arm <qemu-arm@nongnu.org>,
	QEMU Developers <qemu-devel@nongnu.org>,
	Maxim Uvarov <maxim.uvarov@linaro.org>
Subject: Re: [PATCH 03/11] hw/gpio/pl061: Clean up read/write offset handling logic
Date: Fri, 2 Jul 2021 12:45:51 +0100	[thread overview]
Message-ID: <CAFEAcA9n-3-0V4==-j5-vBFsMHtHmXtkctxsyYEVWi-obipRBw@mail.gmail.com> (raw)
In-Reply-To: <52e5cb6e-1be5-cc73-5aab-790c5b9b80bb@amsat.org>

On Fri, 2 Jul 2021 at 12:02, Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>
> Hi Peter,
>
> On 7/2/21 12:40 PM, Peter Maydell wrote:
> > Currently the pl061_read() and pl061_write() functions handle offsets
> > using a combination of three if() statements and a switch().  Clean
> > this up to use just a switch, using case ranges.
> >
> > This requires that instead of catching accesses to the luminary-only
> > registers on a stock PL061 via a check on s->rsvd_start we use
> > an "is this luminary?" check in the cases for each luminary-only
> > register.
> >
> > Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> > ---
> >  hw/gpio/pl061.c | 106 ++++++++++++++++++++++++++++++++++++------------
> >  1 file changed, 81 insertions(+), 25 deletions(-)
> >
> > diff --git a/hw/gpio/pl061.c b/hw/gpio/pl061.c
> > index a6ace88895d..0f5d12e6d5a 100644
> > --- a/hw/gpio/pl061.c
> > +++ b/hw/gpio/pl061.c
> > @@ -55,7 +55,6 @@ struct PL061State {
> >      qemu_irq irq;
> >      qemu_irq out[N_GPIOS];
> >      const unsigned char *id;
> > -    uint32_t rsvd_start; /* reserved area: [rsvd_start, 0xfcc] */
> >  };
> >
> >  static const VMStateDescription vmstate_pl061 = {
> > @@ -151,16 +150,9 @@ static uint64_t pl061_read(void *opaque, hwaddr offset,
> >  {
> >      PL061State *s = (PL061State *)opaque;
> >
> > -    if (offset < 0x400) {
> > -        return s->data & (offset >> 2);
> > -    }
> > -    if (offset >= s->rsvd_start && offset <= 0xfcc) {
> > -        goto err_out;
> > -    }
> > -    if (offset >= 0xfd0 && offset < 0x1000) {
> > -        return s->id[(offset - 0xfd0) >> 2];
> > -    }
> >      switch (offset) {
> > +    case 0x0 ... 0x3fc: /* Data */
> > +        return s->data & (offset >> 2);
>
> Don't we need to set pl061_ops.impl.min/max_access_size = 4
> to keep the same logic?

I think the hardware intends to permit accesses of any width, but only
at 4-byte boundaries. There is a slight behaviour change here:
accesses to 0x3fd, 0x3fe, 0x3ff now fall into the default case (ie error)
rather than being treated like 0x3fc, and similarly accesses to 0xfdd,
0xfde, 0xfdf are errors rather than treated like 0xfdc. But I think
that it's probably more correct to consider those to be errors.

(We could explicitly check and goto err_out if (offset & 3)
right at the top, I suppose.)

-- PMM


  reply	other threads:[~2021-07-02 11:47 UTC|newest]

Thread overview: 29+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-07-02 10:40 [PATCH 00/11] hw/arm: Make virt board secure powerdown/reset work Peter Maydell
2021-07-02 10:40 ` [PATCH 01/11] hw/gpio/gpio_pwr: use shutdown function for reboot Peter Maydell
2021-07-02 10:40 ` [PATCH 02/11] hw/gpio/pl061: Convert DPRINTF to tracepoints Peter Maydell
2021-07-02 10:53   ` Philippe Mathieu-Daudé
2021-07-07  1:19   ` Richard Henderson
2021-07-02 10:40 ` [PATCH 03/11] hw/gpio/pl061: Clean up read/write offset handling logic Peter Maydell
2021-07-02 11:02   ` Philippe Mathieu-Daudé
2021-07-02 11:45     ` Peter Maydell [this message]
2021-07-07  1:25       ` Richard Henderson
2021-07-08  9:39         ` Peter Maydell
2021-07-08 15:07           ` Richard Henderson
2021-07-07  1:21   ` Richard Henderson
2021-07-02 10:40 ` [PATCH 04/11] hw/gpio/pl061: Add tracepoints for register read and write Peter Maydell
2021-07-02 10:55   ` Philippe Mathieu-Daudé
2021-07-07  1:26   ` Richard Henderson
2021-07-02 10:40 ` [PATCH 05/11] hw/gpio/pl061: Document the interface of this device Peter Maydell
2021-07-07  1:26   ` Richard Henderson
2021-07-02 10:40 ` [PATCH 06/11] hw/gpio/pl061: Honour Luminary PL061 PUR and PDR registers Peter Maydell
2021-07-07  1:29   ` Richard Henderson
2021-07-02 10:40 ` [PATCH 07/11] hw/gpio/pl061: Make pullup/pulldown of outputs configurable Peter Maydell
2021-07-07  1:31   ` Richard Henderson
2021-07-02 10:40 ` [PATCH 08/11] hw/arm/virt: Make PL061 GPIO lines pulled low, not high Peter Maydell
2021-07-07  1:32   ` Richard Henderson
2021-07-02 10:40 ` [PATCH 09/11] hw/gpio/pl061: Convert to 3-phase reset and assert GPIO lines correctly on reset Peter Maydell
2021-07-02 10:56   ` Philippe Mathieu-Daudé
2021-07-07  1:33   ` Richard Henderson
2021-07-02 10:40 ` [PATCH 10/11] hw/gpio/pl061: Document a shortcoming in our implementation Peter Maydell
2021-07-02 10:57   ` Philippe Mathieu-Daudé
2021-07-02 10:40 ` [PATCH 11/11] hw/arm/stellaris: Expand comment about handling of OLED chipselect Peter Maydell

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