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From: Peter Maydell <peter.maydell@linaro.org>
Date: Tue, 28 Jan 2014 08:42:21 +0000
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Subject: Re: [Qemu-devel] [PATCH 05/24] target-arm: Add exception level to
 the AArch64 TB flags
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To: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Cc: Laurent Desnogues <laurent.desnogues@gmail.com>, Patch Tracking <patches@linaro.org>, Michael Matz <matz@suse.de>, Alexander Graf <agraf@suse.de>, "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>, Claudio Fontana <claudio.fontana@linaro.org>, Dirk Mueller <dmueller@suse.de>, Will Newton <will.newton@linaro.org>, =?UTF-8?B?QWxleCBCZW5uw6ll?= <alex.bennee@linaro.org>, "kvmarm@lists.cs.columbia.edu" <kvmarm@lists.cs.columbia.edu>, Christoffer Dall <christoffer.dall@linaro.org>, Richard Henderson <rth@twiddle.net>

On 28 January 2014 01:28, Peter Crosthwaite
<peter.crosthwaite@xilinx.com> wrote:
> On Wed, Jan 22, 2014 at 6:12 AM, Peter Maydell <peter.maydell@linaro.org> wrote:
>> We already implicitly rely on the exception level being
>> part of the TB flags for coprocessor access,
>
> Maybe that's the issue? Why not just treat the exception level as
> state like any other and generate the TCG to just check it at
> execution time?

That would be ferociously expensive, because "am I privileged
or not?" is baked into every single guest load or store.
Including privilege level in the tb flags is standard for
every target CPU we have.

thanks
-- PMM