From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50603) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aSo9a-0005tN-K9 for qemu-devel@nongnu.org; Mon, 08 Feb 2016 10:55:07 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aSo9Z-0004yA-GI for qemu-devel@nongnu.org; Mon, 08 Feb 2016 10:55:06 -0500 Received: from mail-vk0-x230.google.com ([2607:f8b0:400c:c05::230]:35749) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aSo9Z-0004wt-8V for qemu-devel@nongnu.org; Mon, 08 Feb 2016 10:55:05 -0500 Received: by mail-vk0-x230.google.com with SMTP id e6so97715606vkh.2 for ; Mon, 08 Feb 2016 07:55:04 -0800 (PST) MIME-Version: 1.0 In-Reply-To: References: From: Peter Maydell Date: Mon, 8 Feb 2016 15:54:45 +0000 Message-ID: Content-Type: text/plain; charset=UTF-8 Subject: Re: [Qemu-devel] Regarding Cortex-A7 CPU definition List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Deepak kumar Raju Cc: QEMU Developers > On Mon, Feb 8, 2016 at 2:21 PM, Deepak kumar Raju wrote: >> I am Deepak. I have a Cortex-A7 board and I am using qemu code from Linaro. >> In Qemu-linaro.git, under .../target-arm/cpu.c, I do not see CPU definitions for Cortex-A7. >> I have few questions: >> >> a)Can you please point to Cortex-A7 CPU definitions? We don't implement a Cortex-A7 in QEMU, because we have no board models that need it. >> b) Can we use the CPU definitions of Cortex-A15 for Cortex-A7? Typically guest code doesn't care about the exact CPU type between the A15 and the A7. If you wanted to add A7 support then starting with the A15 would be a good start. >> c) What would be the diff of Cortex-A7 definitions compared to Cortex-A15? You need to look at the Technical Reference Manual for the two CPUs to determine the difference. As far as QEMU is concerned the things to look at are: * ID register values * supported CPU features * any implementation-specific coprocessor registers ...in other words, all the things we set in the cortex_a15_initfn(). thanks -- PMM