From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33042) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Wio6J-0007Zm-7x for qemu-devel@nongnu.org; Fri, 09 May 2014 12:56:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Wio6D-0003Ra-SU for qemu-devel@nongnu.org; Fri, 09 May 2014 12:56:47 -0400 Received: from mail-la0-f42.google.com ([209.85.215.42]:58460) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Wio6D-0003RV-LK for qemu-devel@nongnu.org; Fri, 09 May 2014 12:56:41 -0400 Received: by mail-la0-f42.google.com with SMTP id el20so72392lab.15 for ; Fri, 09 May 2014 09:56:40 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: References: From: Peter Maydell Date: Fri, 9 May 2014 17:56:20 +0100 Message-ID: Content-Type: text/plain; charset=UTF-8 Subject: Re: [Qemu-devel] [PATCH v3 2/2] ssi: Name the CS GPIO. List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Crosthwaite Cc: Edgar Iglesias , alistai@xilinx.com, QEMU Developers , =?UTF-8?Q?Andreas_F=C3=A4rber?= On 8 May 2014 07:59, Peter Crosthwaite wrote: > To get it out of the default GPIO list. This allows child devices to > use the un-named GPIO namespace without having to be SSI aware. That > is, there is no more need for machines to know about the obscure > policy where GPIO 0 is the SSI chip-select and GPIO 1..N are the > concrete class GPIOs (defined locally as 0..N-1). > > This is most notable is stellaris, which uses a device which has both > SSI and concrete level GPIOs. > > Signed-off-by: Peter Crosthwaite Reviewed-by: Peter Maydell -- PMM