From mboxrd@z Thu Jan  1 00:00:00 1970
Received: from eggs.gnu.org ([2001:4830:134:3::10]:56821)
	by lists.gnu.org with esmtp (Exim 4.71)
	(envelope-from <peter.maydell@linaro.org>) id 1ZZJvJ-00026p-Ls
	for qemu-devel@nongnu.org; Tue, 08 Sep 2015 10:31:02 -0400
Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)
	(envelope-from <peter.maydell@linaro.org>) id 1ZZJvG-0003GW-BP
	for qemu-devel@nongnu.org; Tue, 08 Sep 2015 10:31:01 -0400
Received: from mail-yk0-f170.google.com ([209.85.160.170]:33310)
	by eggs.gnu.org with esmtp (Exim 4.71)
	(envelope-from <peter.maydell@linaro.org>) id 1ZZJvG-0003GS-0U
	for qemu-devel@nongnu.org; Tue, 08 Sep 2015 10:30:58 -0400
Received: by ykei199 with SMTP id i199so121162410yke.0
	for <qemu-devel@nongnu.org>; Tue, 08 Sep 2015 07:30:57 -0700 (PDT)
MIME-Version: 1.0
In-Reply-To: <1441311266-8644-7-git-send-email-edgar.iglesias@gmail.com>
References: <1441311266-8644-1-git-send-email-edgar.iglesias@gmail.com>
	<1441311266-8644-7-git-send-email-edgar.iglesias@gmail.com>
From: Peter Maydell <peter.maydell@linaro.org>
Date: Tue, 8 Sep 2015 15:30:38 +0100
Message-ID: <CAFEAcA_-OK9SnPrQM4ZT3fWO-U9_hG7-reGqhGA10Bt_OGL4mg@mail.gmail.com>
Content-Type: text/plain; charset=UTF-8
Subject: Re: [Qemu-devel] [PATCH v1 06/10] target-arm: Supress TBI for S2
	translations
List-Id: <qemu-devel.nongnu.org>
List-Unsubscribe: <https://lists.nongnu.org/mailman/options/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>
List-Archive: <http://lists.nongnu.org/archive/html/qemu-devel>
List-Post: <mailto:qemu-devel@nongnu.org>
List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help>
List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=subscribe>
To: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
Cc: Edgar Iglesias <edgar.iglesias@xilinx.com>, Sergey Fedorov <serge.fdrv@gmail.com>, =?UTF-8?B?QWxleCBCZW5uw6ll?= <alex.bennee@linaro.org>, QEMU Developers <qemu-devel@nongnu.org>, Alexander Graf <agraf@suse.de>

On 3 September 2015 at 21:14, Edgar E. Iglesias
<edgar.iglesias@gmail.com> wrote:
> From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
>
> Stage-2 MMU translations do not have configurable TBI as
> the top byte is always 0 (48-bit IPAs).
>
> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
> ---
>  target-arm/helper.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index ec19e68..9ea9719 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -6350,7 +6350,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
>          va_size = 64;
>          if (el > 1) {
>              tbi = extract64(tcr->raw_tcr, 20, 1);
> -        } else {
> +        } else if (mmu_idx != ARMMMUIdx_S2NS) {
>              if (extract64(address, 55, 1)) {
>                  tbi = extract64(tcr->raw_tcr, 38, 1);
>              } else {

This doesn't look right. regime_el() for S2NS is 2, so
in this else clause mmu_idx can never be S2NS.

Also "suppress" has two 'p's in it :-)

thanks
-- PMM