From: Peter Maydell <peter.maydell@linaro.org>
To: Palmer Dabbelt <palmer@sifive.com>
Cc: Alistair Francis <Alistair.Francis@wdc.com>,
Alistair Francis <alistair23@gmail.com>,
Michael Clark <mjc@sifive.com>,
QEMU Developers <qemu-devel@nongnu.org>
Subject: Re: [Qemu-devel] [PATCH v1 0/5] Misc RISC-V patches
Date: Thu, 11 Oct 2018 10:34:16 +0100 [thread overview]
Message-ID: <CAFEAcA_-f905hV39yhVypBQzTfocEOPsFvNGK0a=KBm+cKfRCQ@mail.gmail.com> (raw)
In-Reply-To: <mhng-e2fff6d4-8420-48c5-92d9-cc03e16dfa48@palmer-si-x1c4>
On 10 October 2018 at 19:22, Palmer Dabbelt <palmer@sifive.com> wrote:
> On Wed, 10 Oct 2018 11:10:07 PDT (-0700), peter.maydell@linaro.org wrote:
>>
>> On 10 October 2018 at 18:49, Palmer Dabbelt <palmer@sifive.com> wrote:
>>>
>>> we should really
>>> get the ball rolling on our big patch backlog.
>>
>>
>> Yes, please do. Softfreeze is not all that far away and I
>> would strongly prefer not to get an enormous sized pull
>> request at the last minute. The ideal pattern is that
>> code changes come in at a steady rate across the whole
>> of the 'open' part of the development cycle.
>
>
> Ya, sorry, we've been a bit out of it. If I understand correctly, the soft
> freeze is the 30th? If so it's really time to get started, and it looks
> like Michael is busy so I'll have to go figure this out.
Alistair's done the last couple of riscv pullrequests, so it might
be simpler if he keeps doing that, but I'll let you sort that out
between yourselves.
thanks
-- PMM
next prev parent reply other threads:[~2018-10-11 9:34 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-10-08 18:25 [Qemu-devel] [PATCH v1 0/5] Misc RISC-V patches Alistair Francis
2018-10-08 18:25 ` [Qemu-devel] [PATCH v1 1/5] RISC-V: Allow setting and clearing multiple irqs Alistair Francis
2018-10-10 20:03 ` Palmer Dabbelt
2018-10-08 18:25 ` [Qemu-devel] [PATCH v1 2/5] RISC-V: Move non-ops from op_helper to cpu_helper Alistair Francis
2018-10-10 19:07 ` Philippe Mathieu-Daudé
2018-10-10 20:03 ` Palmer Dabbelt
2018-10-08 18:25 ` [Qemu-devel] [PATCH v1 3/5] RISC-V: Update CSR and interrupt definitions Alistair Francis
2018-10-10 20:03 ` Palmer Dabbelt
2018-10-08 18:25 ` [Qemu-devel] [PATCH v1 4/5] RISC-V: Add missing free for plic_hart_config Alistair Francis
2018-10-10 19:10 ` Philippe Mathieu-Daudé
2018-10-10 20:03 ` Palmer Dabbelt
2018-10-08 18:25 ` [Qemu-devel] [PATCH v1 5/5] RISC-V: Don't add NULL bootargs to device-tree Alistair Francis
2018-10-10 19:06 ` Philippe Mathieu-Daudé
2018-10-10 20:03 ` Palmer Dabbelt
2018-10-10 17:49 ` [Qemu-devel] [PATCH v1 0/5] Misc RISC-V patches Palmer Dabbelt
2018-10-10 18:10 ` Peter Maydell
2018-10-10 18:14 ` Alistair
2018-10-10 18:22 ` Palmer Dabbelt
2018-10-11 9:34 ` Peter Maydell [this message]
2018-10-12 0:11 ` Palmer Dabbelt
2018-10-11 20:52 ` Michael Clark
2018-10-12 9:34 ` Peter Maydell
2018-10-15 20:28 ` Palmer Dabbelt
2018-10-16 8:05 ` Peter Maydell
2018-10-16 18:35 ` Palmer Dabbelt
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to='CAFEAcA_-f905hV39yhVypBQzTfocEOPsFvNGK0a=KBm+cKfRCQ@mail.gmail.com' \
--to=peter.maydell@linaro.org \
--cc=Alistair.Francis@wdc.com \
--cc=alistair23@gmail.com \
--cc=mjc@sifive.com \
--cc=palmer@sifive.com \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).