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From: Peter Maydell <peter.maydell@linaro.org>
Date: Sat, 11 Jan 2014 00:01:42 +0000
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Subject: Re: [Qemu-devel] [PATCH 03/10] target-arm: A64: Add decode skeleton
 for SIMD data processing insns
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To: Richard Henderson <rth@twiddle.net>
Cc: Laurent Desnogues <laurent.desnogues@gmail.com>, Patch Tracking <patches@linaro.org>, Michael Matz <matz@suse.de>, Alexander Graf <agraf@suse.de>, QEMU Developers <qemu-devel@nongnu.org>, Claudio Fontana <claudio.fontana@linaro.org>, Dirk Mueller <dmueller@suse.de>, Will Newton <will.newton@linaro.org>, =?UTF-8?B?QWxleCBCZW5uw6ll?= <alex.bennee@linaro.org>, "kvmarm@lists.cs.columbia.edu" <kvmarm@lists.cs.columbia.edu>, Christoffer Dall <christoffer.dall@linaro.org>

On 10 January 2014 19:05, Richard Henderson <rth@twiddle.net> wrote:
> On 01/10/2014 09:12 AM, Peter Maydell wrote:
>>  static void disas_data_proc_simd(DisasContext *s, uint32_t insn)
>>  {
>>      /* Note that this is called with all non-FP cases from
>>       * table C3-6 so it must UNDEF for entries not specifically
>>       * allocated to instructions in that table.
>>       */
>> -    unsupported_encoding(s, insn);
>> +    AArch64DecodeFn *fn = lookup_disas_fn(&data_proc_simd[0], insn);
>> +    if (fn) {
>> +        (fn) (s, insn);
>
> Oh, do you want to CheckFPAdvSIMDEnabled64 here before calling fn?
> Otherwise that's the first thing I noticed missing from patch 4.

We don't currently check that for the FP insns either. Since it's a system
register check and will always pass for usermode emulation I was planning
to leave it for when I did system emulation and wired up the CPACR_EL1.

thanks
-- PMM