From: Peter Maydell <peter.maydell@linaro.org>
To: Richard Henderson <rth@twiddle.net>
Cc: "QEMU Developers" <qemu-devel@nongnu.org>,
"Alex Bennée" <alex.bennee@linaro.org>
Subject: Re: [Qemu-devel] [PATCH 1/2] tcg/aarch64: Fix addsub2 for 0+C
Date: Wed, 7 Dec 2016 18:10:35 +0000 [thread overview]
Message-ID: <CAFEAcA_7kvm41Q-hzWW04ujk+y4jAekhoG9A4yYFSdaoDOgpHw@mail.gmail.com> (raw)
In-Reply-To: <20161207180727.6286-2-rth@twiddle.net>
On 7 December 2016 at 18:07, Richard Henderson <rth@twiddle.net> wrote:
> When al == xzr, we cannot use addi/subi because that encodes xsp.
> Force a zero into the temp register for that (rare) case.
Incidentally I was slightly surprised that the optimisation
pass didn't turn "add2 rlo, rhi, 0, 0, 0, 0" into moves of 0
into rlo and rhi. Constant shifts of xzr in the guest don't
seem worth spending much effort on optimising though :-)
thanks
-- PMM
next prev parent reply other threads:[~2016-12-07 18:12 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-12-07 18:07 [Qemu-devel] [PATCH 0/2] tcg/aarch64 fixes Richard Henderson
2016-12-07 18:07 ` [Qemu-devel] [PATCH 1/2] tcg/aarch64: Fix addsub2 for 0+C Richard Henderson
2016-12-07 18:10 ` Peter Maydell [this message]
2016-12-07 18:15 ` Richard Henderson
2016-12-07 18:07 ` [Qemu-devel] [PATCH 2/2] tcg/aarch64: Fix tcg_out_movi Richard Henderson
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