From: Peter Maydell <peter.maydell@linaro.org>
To: Greg Bellows <greg.bellows@linaro.org>
Cc: Sergey Fedorov <serge.fdrv@gmail.com>,
QEMU Developers <qemu-devel@nongnu.org>,
Fabian Aggeler <aggelerf@ethz.ch>,
"Edgar E. Iglesias" <edgar.iglesias@gmail.com>
Subject: Re: [Qemu-devel] [PATCH v6 02/32] target-arm: add arm_is_secure() function
Date: Mon, 13 Oct 2014 14:41:22 +0200 [thread overview]
Message-ID: <CAFEAcA_8PCvR9pMm+jDFDnKZSjqWwm_WCVpM96UBVvrTBSYFPQ@mail.gmail.com> (raw)
In-Reply-To: <1412957023-11105-3-git-send-email-greg.bellows@linaro.org>
On 10 October 2014 18:03, Greg Bellows <greg.bellows@linaro.org> wrote:
> From: Fabian Aggeler <aggelerf@ethz.ch>
>
> arm_is_secure() function allows to determine CPU security state
> if the CPU implements Security Extensions/EL3.
> arm_is_secure_below_el3() returns true if CPU is in secure state
> below EL3.
>
> Signed-off-by: Sergey Fedorov <s.fedorov@samsung.com>
> Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch>
> Signed-off-by: Greg Bellows <greg.bellows@linaro.org>
>
> ==========
>
> v5 -> v6
> - Broaden CONFIG_USER conditional
> - Merge resulting false returns with common comment
> - Globally change Aarch# to AArch#
> - Replace direct access of env->aarch64 with is_a64()
> ---
> target-arm/cpu.h | 42 ++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 42 insertions(+)
>
> diff --git a/target-arm/cpu.h b/target-arm/cpu.h
> index 81fffd2..4f6db0f 100644
> --- a/target-arm/cpu.h
> +++ b/target-arm/cpu.h
> @@ -753,6 +753,48 @@ static inline int arm_feature(CPUARMState *env, int feature)
> return (env->features & (1ULL << feature)) != 0;
> }
>
> +#if !defined(CONFIG_USER_ONLY)
> +/* Return true if exception level below EL3 is in secure state */
This is still missing the clarifying comment I was hoping for.
Make this:
/* Return true if exception levels below EL3 are in secure state,
* or would be following an exception return to that level.
* Unlike arm_is_secure() (which is alvays a question about the
* _current_ state of the CPU) this doesn't care about the current
* EL or mode.
*/
and then you can add my reviewed-by tag.
thanks
-- PMM
next prev parent reply other threads:[~2014-10-13 12:41 UTC|newest]
Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-10-10 16:03 [Qemu-devel] [PATCH v6 00/32] target-arm: add Security Extensions for CPUs Greg Bellows
2014-10-10 16:03 ` [Qemu-devel] [PATCH v6 01/32] target-arm: increase arrays of registers R13 & R14 Greg Bellows
2014-10-13 12:31 ` Peter Maydell
2014-10-10 16:03 ` [Qemu-devel] [PATCH v6 02/32] target-arm: add arm_is_secure() function Greg Bellows
2014-10-13 12:41 ` Peter Maydell [this message]
2014-10-10 16:03 ` [Qemu-devel] [PATCH v6 03/32] target-arm: reject switching to monitor mode Greg Bellows
2014-10-13 12:58 ` Peter Maydell
2014-10-10 16:03 ` [Qemu-devel] [PATCH v6 04/32] target-arm: rename arm_current_pl to arm_current_el Greg Bellows
2014-10-13 13:00 ` Peter Maydell
2014-10-10 16:03 ` [Qemu-devel] [PATCH v6 05/32] target-arm: make arm_current_el() return EL3 Greg Bellows
2014-10-13 13:04 ` Peter Maydell
2014-10-10 16:03 ` [Qemu-devel] [PATCH v6 06/32] target-arm: A32: Emulate the SMC instruction Greg Bellows
2014-10-13 13:06 ` Peter Maydell
2014-10-13 13:13 ` Greg Bellows
2014-10-13 13:36 ` Peter Maydell
2014-10-13 13:56 ` Greg Bellows
2014-10-10 16:03 ` [Qemu-devel] [PATCH v6 07/32] target-arm: extend async excp masking Greg Bellows
2014-10-10 16:03 ` [Qemu-devel] [PATCH v6 08/32] target-arm: add async excp target_el function Greg Bellows
2014-10-10 16:03 ` [Qemu-devel] [PATCH v6 09/32] target-arm: add banked register accessors Greg Bellows
2014-10-10 16:03 ` [Qemu-devel] [PATCH v6 10/32] target-arm: add non-secure Translation Block flag Greg Bellows
2014-10-10 16:03 ` [Qemu-devel] [PATCH v6 11/32] target-arm: add CPREG secure state support Greg Bellows
2014-10-17 1:32 ` Edgar E. Iglesias
2014-10-17 13:37 ` Greg Bellows
2014-10-17 15:20 ` Greg Bellows
2014-10-17 15:27 ` Laurent Desnogues
2014-10-17 15:30 ` Greg Bellows
2014-10-17 19:12 ` Greg Bellows
2014-10-10 16:03 ` [Qemu-devel] [PATCH v6 12/32] target-arm: add secure state bit to CPREG hash Greg Bellows
2014-10-10 16:03 ` [Qemu-devel] [PATCH v6 13/32] target-arm: insert AArch32 cpregs twice into hashtable Greg Bellows
2014-10-10 16:03 ` [Qemu-devel] [PATCH v6 14/32] target-arm: move AArch32 SCR into security reglist Greg Bellows
2014-10-10 16:03 ` [Qemu-devel] [PATCH v6 15/32] target-arm: implement IRQ/FIQ routing to Monitor mode Greg Bellows
2014-10-10 16:03 ` [Qemu-devel] [PATCH v6 16/32] target-arm: respect SCR.FW, SCR.AW and SCTLR.NMFI Greg Bellows
2014-10-10 16:03 ` [Qemu-devel] [PATCH v6 17/32] target-arm: add NSACR register Greg Bellows
2014-10-10 16:03 ` [Qemu-devel] [PATCH v6 18/32] target-arm: add SDER definition Greg Bellows
2014-10-10 16:03 ` [Qemu-devel] [PATCH v6 19/32] target-arm: add MVBAR support Greg Bellows
2014-10-10 16:03 ` [Qemu-devel] [PATCH v6 20/32] target-arm: add SCTLR_EL3 and make SCTLR banked Greg Bellows
2014-10-10 16:03 ` [Qemu-devel] [PATCH v6 21/32] target-arm: make CSSELR banked Greg Bellows
2014-10-10 16:03 ` [Qemu-devel] [PATCH v6 22/32] target-arm: add TTBR0_EL3 and make TTBR0/1 banked Greg Bellows
2014-10-10 16:03 ` [Qemu-devel] [PATCH v6 23/32] target-arm: add TCR_EL3 and make TTBCR banked Greg Bellows
2014-10-10 16:03 ` [Qemu-devel] [PATCH v6 24/32] target-arm: make c2_mask and c2_base_mask banked Greg Bellows
2014-10-10 16:03 ` [Qemu-devel] [PATCH v6 25/32] target-arm: make DACR banked Greg Bellows
2014-10-10 16:03 ` [Qemu-devel] [PATCH v6 26/32] target-arm: make IFSR banked Greg Bellows
2014-10-10 16:03 ` [Qemu-devel] [PATCH v6 27/32] target-arm: make DFSR banked Greg Bellows
2014-10-10 16:03 ` [Qemu-devel] [PATCH v6 28/32] target-arm: make IFAR/DFAR banked Greg Bellows
2014-10-10 16:03 ` [Qemu-devel] [PATCH v6 29/32] target-arm: make PAR banked Greg Bellows
2014-10-10 16:03 ` [Qemu-devel] [PATCH v6 30/32] target-arm: make c13 cp regs banked (FCSEIDR, ...) Greg Bellows
2014-10-15 3:17 ` Edgar E. Iglesias
2014-10-16 18:20 ` Greg Bellows
2014-10-10 16:03 ` [Qemu-devel] [PATCH v6 31/32] target-arm: make MAIR0/1 banked Greg Bellows
2014-10-10 16:03 ` [Qemu-devel] [PATCH v6 32/32] target-arm: add cpu feature EL3 to CPUs with Security Extensions Greg Bellows
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