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Wed, 12 Mar 2025 07:22:50 -0700 (PDT) MIME-Version: 1.0 References: <20250311153717.206129-1-pbonzini@redhat.com> In-Reply-To: From: Peter Maydell Date: Wed, 12 Mar 2025 14:22:37 +0000 X-Gm-Features: AQ5f1Jo0ih_I4s9hBZOC3oKtkSGRthAMEw4vb6qqqYkfDgkz0_NZI0P-gaGpWDI Message-ID: Subject: Re: [PATCH] Revert "hw/char/pl011: Warn when using disabled receiver" To: Paolo Bonzini Cc: qemu-devel@nongnu.org, =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::b2c; envelope-from=peter.maydell@linaro.org; helo=mail-yb1-xb2c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Wed, 12 Mar 2025 at 13:36, Peter Maydell wrot= e: > > On Tue, 11 Mar 2025 at 15:37, Paolo Bonzini wrote: > > > > The guest does not control whether characters are sent on the UART. > > Sending them before the guest happens to boot will now result in a > > "guest error" log entry that is only because of timing, even if the > > guest _would_ later setup the receiver correctly. > > > > This reverts commit abf2b6a028670bd2890bb3aee7e103fe53e4b0df, apart > > from adding the comment. > > > > Cc: Philippe Mathieu-Daud=C3=A9 > > Cc: Peter Maydell > > Signed-off-by: Paolo Bonzini > > --- > > hw/char/pl011.c | 12 ++---------- > > 1 file changed, 2 insertions(+), 10 deletions(-) > > > > diff --git a/hw/char/pl011.c b/hw/char/pl011.c > > index 23a9db8c57c..efca8baecd7 100644 > > --- a/hw/char/pl011.c > > +++ b/hw/char/pl011.c > > @@ -85,7 +85,6 @@ DeviceState *pl011_create(hwaddr addr, qemu_irq irq, = Chardev *chr) > > #define CR_OUT1 (1 << 12) > > #define CR_RTS (1 << 11) > > #define CR_DTR (1 << 10) > > -#define CR_RXE (1 << 9) > > #define CR_TXE (1 << 8) > > #define CR_LBE (1 << 7) > > #define CR_UARTEN (1 << 0) > > @@ -490,16 +489,9 @@ static int pl011_can_receive(void *opaque) > > unsigned fifo_depth =3D pl011_get_fifo_depth(s); > > unsigned fifo_available =3D fifo_depth - s->read_count; > > > > - if (!(s->cr & CR_UARTEN)) { > > - qemu_log_mask(LOG_GUEST_ERROR, > > - "PL011 receiving data on disabled UART\n"); > > - } > > - if (!(s->cr & CR_RXE)) { > > - qemu_log_mask(LOG_GUEST_ERROR, > > - "PL011 receiving data on disabled RX UART\n"); > > - } > > + /* Should check enable and return 0? */ > > We decided deliberately not to check the enable and return 0 > here, as described in the commit message of abf2b6a028670bd: > we think there's too likely to be existing works-on-QEMU code > out there that doesn't ever set the enable bits. > > Otherwise, yes, agreed with the revert. I've applied this to target-arm.next with the comment expanded (and I left the define of CR_RXE in too): + /* + * In theory we should check the UART and RX enable bits here and + * return 0 if they are not set (so the guest can't receive data + * until you have enabled the UART). In practice we suspect there + * is at least some guest code out there which has been tested only + * on QEMU and which never bothers to enable the UART because we + * historically never enforced that. So we effectively keep the + * UART continuously enabled regardless of the enable bits. + */ thanks -- PMM