From: Peter Maydell <peter.maydell@linaro.org>
To: Zheyu Ma <zheyuma97@gmail.com>
Cc: "Igor Mitsyanko" <i.mitsyanko@gmail.com>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>,
qemu-arm@nongnu.org, qemu-devel@nongnu.org
Subject: Re: [PATCH v3] hw/misc: Set valid access size for Exynos4210 RNG
Date: Fri, 21 Jun 2024 15:54:13 +0100 [thread overview]
Message-ID: <CAFEAcA_BB7Lw357iLZZbCfvhnH+8G2qyfVrs8dhP_i-mnwnvOw@mail.gmail.com> (raw)
In-Reply-To: <20240618163701.3204975-1-zheyuma97@gmail.com>
On Tue, 18 Jun 2024 at 17:37, Zheyu Ma <zheyuma97@gmail.com> wrote:
>
> The Exynos4210 RNG module requires 32-bit (4-byte) accesses to its registers.
> According to the User Manual Section 25.3[1], the registers for RNG operations
> are 32-bit. This change ensures that the memory region operations for the
> RNG module enforce the correct access sizes, preventing invalid memory accesses.
>
> [1] http://www.mediafire.com/view/8ly2fqls3c9c31c/Exynos_4412_SCP_Users_Manual_Ver.0.10.00_Preliminary0.pdf
>
> Reproducer:
> cat << EOF | qemu-system-aarch64 -display none \
> -machine accel=qtest, -m 512M -machine smdkc210 -qtest stdio
> readb 0x10830454
> EOF
>
> Suggested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> Signed-off-by: Zheyu Ma <zheyuma97@gmail.com>
> ---
> Changes in v3:
> - point to the device specification
Applied to target-arm.next, thanks.
-- PMM
prev parent reply other threads:[~2024-06-21 14:55 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-06-18 16:37 [PATCH v3] hw/misc: Set valid access size for Exynos4210 RNG Zheyu Ma
2024-06-21 14:54 ` Peter Maydell [this message]
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