From: Peter Maydell <peter.maydell@linaro.org>
To: P J P <ppandit@redhat.com>
Cc: Qemu Developers <qemu-devel@nongnu.org>,
Wjjzhang <wjjzhang@tencent.com>, Jiang Xin <jiangxin1@huawei.com>,
Prasad J Pandit <pjp@fedoraproject.org>,
Alistair Francis <alistair.francis@xilinx.com>,
"Edgar E. Iglesias" <edgar.iglesias@gmail.com>
Subject: Re: [Qemu-devel] [PATCH 0/2] sd: sdhci: correct transfer mode register usage
Date: Tue, 7 Feb 2017 17:29:43 +0000 [thread overview]
Message-ID: <CAFEAcA_GoD3h2tfM7R5mBQPV9V4bCkA5oKL9EYXiaGq2Gbd3DQ@mail.gmail.com> (raw)
In-Reply-To: <20170131122416.10284-1-ppandit@redhat.com>
On 31 January 2017 at 12:24, P J P <ppandit@redhat.com> wrote:
> From: Prasad J Pandit <pjp@fedoraproject.org>
>
> Hello,
>
> In SDHCI emulation, the 'Block Count Enable' bit of the Transfer Mode
> register is used to control 's->blkcnt' value. One, this bit is not
> relevant in single block transfers. Second, Transfer Mode register
> value could be set such that 's->blkcnt' would not see an update
> during multi block transfers. Thus leading to an infinite loop.
>
> This patch set attempts to correct 'Block Count Enable' bit usage.
Edgar, Alistair: the zynq models are our major SDHCI user -- would
you like to have a look at this patchset, please?
thanks
-- PMM
next prev parent reply other threads:[~2017-02-07 17:30 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-01-31 12:24 [Qemu-devel] [PATCH 0/2] sd: sdhci: correct transfer mode register usage P J P
2017-01-31 12:24 ` [Qemu-devel] [PATCH 1/2] sd: sdhci: check transfer mode register in multi block transfer P J P
2017-02-07 23:12 ` Alistair Francis
2017-02-08 5:17 ` P J P
2017-01-31 12:24 ` [Qemu-devel] [PATCH 2/2] sd: sdhci: block count enable not relevant in single " P J P
2017-02-07 23:15 ` Alistair Francis
2017-02-06 7:55 ` [Qemu-devel] [PATCH 0/2] sd: sdhci: correct transfer mode register usage P J P
2017-02-07 17:29 ` Peter Maydell [this message]
2017-02-07 19:12 ` P J P
2017-02-07 21:57 ` Alistair Francis
2017-02-08 5:06 ` P J P
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