From: Peter Maydell <peter.maydell@linaro.org>
To: Jean-Philippe Brucker <jean-philippe@linaro.org>
Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org
Subject: Re: [PATCH] hw/arm/virt: fix GIC maintenance IRQ registration
Date: Fri, 10 Nov 2023 10:19:30 +0000 [thread overview]
Message-ID: <CAFEAcA_Jja7MT_cSiEJ2it+wG7LnUXfnuoo1vmoUf1-+KSgtAA@mail.gmail.com> (raw)
In-Reply-To: <20231110090557.3219206-2-jean-philippe@linaro.org>
On Fri, 10 Nov 2023 at 09:07, Jean-Philippe Brucker
<jean-philippe@linaro.org> wrote:
>
> Since commit 9036e917f8 ("{include/}hw/arm: refactor virt PPI logic"),
> GIC maintenance IRQ registration fails on arm64:
>
> [ 0.979743] kvm [1]: Cannot register interrupt 9
>
> That commit re-defined VIRTUAL_PMU_IRQ to be a INTID but missed a case
> where the maintenance IRQ is actually referred by its PPI index. Just
> like commit fa68ecb330db ("hw/arm/virt: fix PMU IRQ registration"), use
> INITID_TO_PPI(). A search of "GIC_FDT_IRQ_TYPE_PPI" indicates that there
> shouldn't be more similar issues.
>
> Fixes: 9036e917f8 ("{include/}hw/arm: refactor virt PPI logic")
> Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Isn't this already fixed by commit fa68ecb330dbd ?
thanks
-- PMM
next prev parent reply other threads:[~2023-11-10 10:20 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-10 9:05 [PATCH] hw/arm/virt: fix GIC maintenance IRQ registration Jean-Philippe Brucker
2023-11-10 10:19 ` Peter Maydell [this message]
2023-11-10 11:45 ` Jean-Philippe Brucker
2023-11-13 13:14 ` Peter Maydell
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