From: Peter Maydell <peter.maydell@linaro.org>
To: QEMU Developers <qemu-devel@nongnu.org>,
"Michael S. Tsirkin" <mst@redhat.com>,
Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
Subject: QEMU PCI subsystem: what code is responsible for making accesses to non-mapped addresses read as -1?
Date: Fri, 19 Mar 2021 12:35:31 +0000 [thread overview]
Message-ID: <CAFEAcA_M4zK1aLdO2QdOUgNROTLdHUwLHnCKoUT1BpTcF-cTMw@mail.gmail.com> (raw)
I'm looking at a bug reported against the QEMU arm virt board's pci-gpex
PCI controller: https://bugs.launchpad.net/qemu/+bug/1918917
where an attempt to write to an address within the PCI IO window
where the guest hasn't mapped a BAR causes a CPU exception rather than
(what I believe is) the PCI-required behaviour of writes-ignored, reads
return -1.
What in the QEMU PCI code is responsible for giving the PCI-spec
behaviour for accesses to the PCI IO and memory windows where there
is no BAR? I was expecting the generic PCI code to map a background
memory region over the whole window to do this, but it looks like it
doesn't...
thanks
-- PMM
next reply other threads:[~2021-03-19 12:37 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-19 12:35 Peter Maydell [this message]
2021-03-19 14:14 ` QEMU PCI subsystem: what code is responsible for making accesses to non-mapped addresses read as -1? Philippe Mathieu-Daudé
2021-03-19 21:13 ` Laszlo Ersek
2021-03-20 18:58 ` Michael S. Tsirkin
2021-03-20 20:40 ` Peter Maydell
2021-03-20 21:50 ` Michael S. Tsirkin
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