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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Igor R , QEMU Developers , Victor CLEMENT , "open list:ARM TCG CPUs" , Pavel Dovgaluk , Paolo Bonzini Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Tue, 28 Jul 2020 at 15:10, Alex Benn=C3=A9e wro= te: > > Otherwise we have an unfortunate interaction with -count sleep=3Doff > which means we fast forward time when we don't need to. The easiest > way to trigger it was to attach to the gdbstub and place a break point > at the timers IRQ routine. Once the timer fired setting the next event > at INT_MAX then qemu_start_warp_timer would skip to the end. > > Signed-off-by: Alex Benn=C3=A9e > --- > target/arm/helper.c | 35 ++++++++++++++++++++++------------- > 1 file changed, 22 insertions(+), 13 deletions(-) > > diff --git a/target/arm/helper.c b/target/arm/helper.c > index c69a2baf1d3..ec1b84cf0fd 100644 > --- a/target/arm/helper.c > +++ b/target/arm/helper.c > @@ -2683,7 +2683,7 @@ static void gt_recalc_timer(ARMCPU *cpu, int timeri= dx) > uint64_t count =3D gt_get_countervalue(&cpu->env); > /* Note that this must be unsigned 64 bit arithmetic: */ > int istatus =3D count - offset >=3D gt->cval; > - uint64_t nexttick; > + uint64_t nexttick =3D 0; > int irqstate; > > gt->ctl =3D deposit32(gt->ctl, 2, 1, istatus); > @@ -2692,21 +2692,30 @@ static void gt_recalc_timer(ARMCPU *cpu, int time= ridx) > qemu_set_irq(cpu->gt_timer_outputs[timeridx], irqstate); > > if (istatus) { > - /* Next transition is when count rolls back over to zero */ > - nexttick =3D UINT64_MAX; > + /* > + * The IRQ status of the timer will persist until: > + * - CVAL is changed or > + * - ENABLE is changed > + * > + * There is no point re-arming the timer for some far > + * flung future - currently it just is. > + */ > + timer_del(cpu->gt_timer[timeridx]); Why do we delete the timer for this case of "next time we need to know is massively in the future"... > } else { > /* Next transition is when we hit cval */ > nexttick =3D gt->cval + offset; > - } > - /* Note that the desired next expiry time might be beyond the > - * signed-64-bit range of a QEMUTimer -- in this case we just > - * set the timer for as far in the future as possible. When the > - * timer expires we will reset the timer for any remaining perio= d. > - */ > - if (nexttick > INT64_MAX / gt_cntfrq_period_ns(cpu)) { > - timer_mod_ns(cpu->gt_timer[timeridx], INT64_MAX); > - } else { > - timer_mod(cpu->gt_timer[timeridx], nexttick); > + > + /* > + * It is possible the next tick is beyond the > + * signed-64-bit range of a QEMUTimer but currently the > + * timer system doesn't support a run time of more the 292 > + * odd years so we set it to INT_MAX in this case. > + */ > + if (nexttick > INT64_MAX / gt_cntfrq_period_ns(cpu)) { > + timer_mod_ns(cpu->gt_timer[timeridx], INT64_MAX); ...but here we handle the similar case by "set a timeout for INT64_MAX" ? > + } else { > + timer_mod(cpu->gt_timer[timeridx], nexttick); > + } > } > trace_arm_gt_recalc(timeridx, irqstate, nexttick); > } else { > -- thanks -- PMM