From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55457) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fL5uJ-0001o4-Cb for qemu-devel@nongnu.org; Tue, 22 May 2018 07:56:48 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fL5uI-0003Bc-9u for qemu-devel@nongnu.org; Tue, 22 May 2018 07:56:47 -0400 Received: from mail-oi0-x242.google.com ([2607:f8b0:4003:c06::242]:41810) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fL5uI-0003B4-4l for qemu-devel@nongnu.org; Tue, 22 May 2018 07:56:46 -0400 Received: by mail-oi0-x242.google.com with SMTP id 11-v6so15914124ois.8 for ; Tue, 22 May 2018 04:56:45 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: <5c004b51-6d28-58e8-2674-0df659c51e65@redhat.com> References: <20180521140402.23318-1-peter.maydell@linaro.org> <20180521140402.23318-19-peter.maydell@linaro.org> <5c004b51-6d28-58e8-2674-0df659c51e65@redhat.com> From: Peter Maydell Date: Tue, 22 May 2018 12:56:24 +0100 Message-ID: Content-Type: text/plain; charset="UTF-8" Subject: Re: [Qemu-devel] [PATCH 18/27] hw/misc/tz-mpc.c: Implement the Arm TrustZone Memory Protection Controller List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Auger Eric Cc: qemu-arm , QEMU Developers , Paolo Bonzini , Richard Henderson , =?UTF-8?B?QWxleCBCZW5uw6ll?= , "patches@linaro.org" On 22 May 2018 at 12:30, Auger Eric wrote: > Hi Peter, > > On 05/21/2018 04:03 PM, Peter Maydell wrote: >> Implement the Arm TrustZone Memory Protection Controller, which sits >> in front of RAM and allows secure software to configure it to either >> pass through or reject transactions. >> >> We implement the MPC as a QEMU IOMMU, which will direct transactions >> either through to the devices and memory behind it or to a special >> "never works" AddressSpace if they are blocked. >> >> This initial commit implements the skeleton of the device: >> * it always permits accesses >> * it doesn't implement most of the registers >> * it doesn't implement the interrupt or other behaviour >> for blocked transactions >> >> Signed-off-by: Peter Maydell > > this patch does not seem to apply on master. Clash in the MAINTAINERS file? There's a dependency on another MAINTAINERS patch, see the Based-on: line in the cover letter. thanks -- PMM