* [PATCH v2 01/17] target/arm: Add isar_feature_aa32_vfp_simd
2020-02-24 22:22 [PATCH v2 00/17] target/arm: vfp feature and decodetree cleanup Richard Henderson
@ 2020-02-24 22:22 ` Richard Henderson
2020-02-25 13:18 ` Peter Maydell
2020-02-24 22:22 ` [PATCH v2 02/17] target/arm: Rename isar_feature_aa32_fpdp_v2 Richard Henderson
` (16 subsequent siblings)
17 siblings, 1 reply; 29+ messages in thread
From: Richard Henderson @ 2020-02-24 22:22 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, qemu-arm
Use this in the places that were checking ARM_FEATURE_VFP, and
are obviously testing for the existance of the register set
as opposed to testing for some particular instruction extension.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/cpu.h | 9 +++++++++
hw/intc/armv7m_nvic.c | 20 ++++++++++----------
linux-user/arm/signal.c | 4 ++--
target/arm/arch_dump.c | 11 ++++++-----
target/arm/cpu.c | 4 ++--
target/arm/helper.c | 4 ++--
target/arm/m_helper.c | 11 ++++++-----
7 files changed, 37 insertions(+), 26 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 65171cb30e..a128d48d40 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3450,6 +3450,15 @@ static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id)
return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1;
}
+static inline bool isar_feature_aa32_vfp_simd(const ARMISARegisters *id)
+{
+ /*
+ * Return true if either VFP or SIMD is implemented.
+ * In this case, a minimum of VFP w/ D0-D15.
+ */
+ return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) > 0;
+}
+
static inline bool isar_feature_aa32_simd_r32(const ARMISARegisters *id)
{
/* Return true if D16-D31 are implemented */
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index 22a43e4984..a62587eb3f 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -1262,12 +1262,12 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
case 0xd84: /* CSSELR */
return cpu->env.v7m.csselr[attrs.secure];
case 0xd88: /* CPACR */
- if (!arm_feature(&cpu->env, ARM_FEATURE_VFP)) {
+ if (!cpu_isar_feature(aa32_vfp_simd, cpu)) {
return 0;
}
return cpu->env.v7m.cpacr[attrs.secure];
case 0xd8c: /* NSACR */
- if (!attrs.secure || !arm_feature(&cpu->env, ARM_FEATURE_VFP)) {
+ if (!attrs.secure || !cpu_isar_feature(aa32_vfp_simd, cpu)) {
return 0;
}
return cpu->env.v7m.nsacr;
@@ -1417,7 +1417,7 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
}
return cpu->env.v7m.sfar;
case 0xf34: /* FPCCR */
- if (!arm_feature(&cpu->env, ARM_FEATURE_VFP)) {
+ if (!cpu_isar_feature(aa32_vfp_simd, cpu)) {
return 0;
}
if (attrs.secure) {
@@ -1444,12 +1444,12 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
return value;
}
case 0xf38: /* FPCAR */
- if (!arm_feature(&cpu->env, ARM_FEATURE_VFP)) {
+ if (!cpu_isar_feature(aa32_vfp_simd, cpu)) {
return 0;
}
return cpu->env.v7m.fpcar[attrs.secure];
case 0xf3c: /* FPDSCR */
- if (!arm_feature(&cpu->env, ARM_FEATURE_VFP)) {
+ if (!cpu_isar_feature(aa32_vfp_simd, cpu)) {
return 0;
}
return cpu->env.v7m.fpdscr[attrs.secure];
@@ -1711,13 +1711,13 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
}
break;
case 0xd88: /* CPACR */
- if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) {
+ if (cpu_isar_feature(aa32_vfp_simd, cpu)) {
/* We implement only the Floating Point extension's CP10/CP11 */
cpu->env.v7m.cpacr[attrs.secure] = value & (0xf << 20);
}
break;
case 0xd8c: /* NSACR */
- if (attrs.secure && arm_feature(&cpu->env, ARM_FEATURE_VFP)) {
+ if (attrs.secure && cpu_isar_feature(aa32_vfp_simd, cpu)) {
/* We implement only the Floating Point extension's CP10/CP11 */
cpu->env.v7m.nsacr = value & (3 << 10);
}
@@ -1951,7 +1951,7 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
break;
}
case 0xf34: /* FPCCR */
- if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) {
+ if (cpu_isar_feature(aa32_vfp_simd, cpu)) {
/* Not all bits here are banked. */
uint32_t fpccr_s;
@@ -2005,13 +2005,13 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
}
break;
case 0xf38: /* FPCAR */
- if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) {
+ if (cpu_isar_feature(aa32_vfp_simd, cpu)) {
value &= ~7;
cpu->env.v7m.fpcar[attrs.secure] = value;
}
break;
case 0xf3c: /* FPDSCR */
- if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) {
+ if (cpu_isar_feature(aa32_vfp_simd, cpu)) {
value &= 0x07c00000;
cpu->env.v7m.fpdscr[attrs.secure] = value;
}
diff --git a/linux-user/arm/signal.c b/linux-user/arm/signal.c
index b0e753801b..d96fc27ce1 100644
--- a/linux-user/arm/signal.c
+++ b/linux-user/arm/signal.c
@@ -346,7 +346,7 @@ static void setup_sigframe_v2(struct target_ucontext_v2 *uc,
setup_sigcontext(&uc->tuc_mcontext, env, set->sig[0]);
/* Save coprocessor signal frame. */
regspace = uc->tuc_regspace;
- if (arm_feature(env, ARM_FEATURE_VFP)) {
+ if (cpu_isar_feature(aa32_vfp_simd, env_archcpu(env))) {
regspace = setup_sigframe_v2_vfp(regspace, env);
}
if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
@@ -671,7 +671,7 @@ static int do_sigframe_return_v2(CPUARMState *env,
/* Restore coprocessor signal frame */
regspace = uc->tuc_regspace;
- if (arm_feature(env, ARM_FEATURE_VFP)) {
+ if (cpu_isar_feature(aa32_vfp_simd, env_archcpu(env))) {
regspace = restore_sigframe_v2_vfp(env, regspace);
if (!regspace) {
return 1;
diff --git a/target/arm/arch_dump.c b/target/arm/arch_dump.c
index 2345dec3c2..7693e17e96 100644
--- a/target/arm/arch_dump.c
+++ b/target/arm/arch_dump.c
@@ -363,9 +363,11 @@ int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
int cpuid, void *opaque)
{
struct arm_note note;
- CPUARMState *env = &ARM_CPU(cs)->env;
+ ARMCPU *cpu = ARM_CPU(cs);
+ CPUARMState *env = &cpu->env;
DumpState *s = opaque;
- int ret, i, fpvalid = !!arm_feature(env, ARM_FEATURE_VFP);
+ int ret, i;
+ bool fpvalid = cpu_isar_feature(aa32_vfp_simd, cpu);
arm_note_init(¬e, s, "CORE", 5, NT_PRSTATUS, sizeof(note.prstatus));
@@ -444,7 +446,6 @@ int cpu_get_dump_info(ArchDumpInfo *info,
ssize_t cpu_get_note_size(int class, int machine, int nr_cpus)
{
ARMCPU *cpu = ARM_CPU(first_cpu);
- CPUARMState *env = &cpu->env;
size_t note_size;
if (class == ELFCLASS64) {
@@ -452,12 +453,12 @@ ssize_t cpu_get_note_size(int class, int machine, int nr_cpus)
note_size += AARCH64_PRFPREG_NOTE_SIZE;
#ifdef TARGET_AARCH64
if (cpu_isar_feature(aa64_sve, cpu)) {
- note_size += AARCH64_SVE_NOTE_SIZE(env);
+ note_size += AARCH64_SVE_NOTE_SIZE(&cpu->env);
}
#endif
} else {
note_size = ARM_PRSTATUS_NOTE_SIZE;
- if (arm_feature(env, ARM_FEATURE_VFP)) {
+ if (cpu_isar_feature(aa32_vfp_simd, cpu)) {
note_size += ARM_VFP_NOTE_SIZE;
}
}
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 2eadf4dcb8..be4c2a1253 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -293,7 +293,7 @@ static void arm_cpu_reset(CPUState *s)
env->v7m.ccr[M_REG_S] |= R_V7M_CCR_UNALIGN_TRP_MASK;
}
- if (arm_feature(env, ARM_FEATURE_VFP)) {
+ if (cpu_isar_feature(aa32_vfp_simd, cpu)) {
env->v7m.fpccr[M_REG_NS] = R_V7M_FPCCR_ASPEN_MASK;
env->v7m.fpccr[M_REG_S] = R_V7M_FPCCR_ASPEN_MASK |
R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK;
@@ -1011,7 +1011,7 @@ static void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags)
int numvfpregs = 0;
if (cpu_isar_feature(aa32_simd_r32, cpu)) {
numvfpregs = 32;
- } else if (arm_feature(env, ARM_FEATURE_VFP)) {
+ } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) {
numvfpregs = 16;
}
for (i = 0; i < numvfpregs; i++) {
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 79db169e04..8841cc7fde 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -894,7 +894,7 @@ static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri,
* ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP.
* TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell.
*/
- if (arm_feature(env, ARM_FEATURE_VFP)) {
+ if (cpu_isar_feature(aa32_vfp_simd, env_archcpu(env))) {
/* VFP coprocessor: cp10 & cp11 [23:20] */
mask |= (1 << 31) | (1 << 30) | (0xf << 20);
@@ -7814,7 +7814,7 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
} else if (cpu_isar_feature(aa32_simd_r32, cpu)) {
gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
35, "arm-vfp3.xml", 0);
- } else if (arm_feature(env, ARM_FEATURE_VFP)) {
+ } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) {
gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
19, "arm-vfp.xml", 0);
}
diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
index 33d414a684..5e8a795d20 100644
--- a/target/arm/m_helper.c
+++ b/target/arm/m_helper.c
@@ -738,7 +738,8 @@ static uint32_t v7m_integrity_sig(CPUARMState *env, uint32_t lr)
*/
uint32_t sig = 0xfefa125a;
- if (!arm_feature(env, ARM_FEATURE_VFP) || (lr & R_V7M_EXCRET_FTYPE_MASK)) {
+ if (!cpu_isar_feature(aa32_vfp_simd, env_archcpu(env))
+ || (lr & R_V7M_EXCRET_FTYPE_MASK)) {
sig |= 1;
}
return sig;
@@ -841,7 +842,7 @@ static void v7m_exception_taken(ARMCPU *cpu, uint32_t lr, bool dotailchain,
if (dotailchain) {
/* Sanitize LR FType and PREFIX bits */
- if (!arm_feature(env, ARM_FEATURE_VFP)) {
+ if (!cpu_isar_feature(aa32_vfp_simd, cpu)) {
lr |= R_V7M_EXCRET_FTYPE_MASK;
}
lr = deposit32(lr, 24, 8, 0xff);
@@ -1373,7 +1374,7 @@ static void do_v7m_exception_exit(ARMCPU *cpu)
ftype = excret & R_V7M_EXCRET_FTYPE_MASK;
- if (!arm_feature(env, ARM_FEATURE_VFP) && !ftype) {
+ if (!ftype && !cpu_isar_feature(aa32_vfp_simd, cpu)) {
qemu_log_mask(LOG_GUEST_ERROR, "M profile: zero FTYPE in exception "
"exit PC value 0x%" PRIx32 " is UNPREDICTABLE "
"if FPU not present\n",
@@ -2450,7 +2451,7 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val)
* SFPA is RAZ/WI from NS. FPCA is RO if NSACR.CP10 == 0,
* RES0 if the FPU is not present, and is stored in the S bank
*/
- if (arm_feature(env, ARM_FEATURE_VFP) &&
+ if (cpu_isar_feature(aa32_vfp_simd, env_archcpu(env)) &&
extract32(env->v7m.nsacr, 10, 1)) {
env->v7m.control[M_REG_S] &= ~R_V7M_CONTROL_FPCA_MASK;
env->v7m.control[M_REG_S] |= val & R_V7M_CONTROL_FPCA_MASK;
@@ -2565,7 +2566,7 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val)
env->v7m.control[env->v7m.secure] &= ~R_V7M_CONTROL_NPRIV_MASK;
env->v7m.control[env->v7m.secure] |= val & R_V7M_CONTROL_NPRIV_MASK;
}
- if (arm_feature(env, ARM_FEATURE_VFP)) {
+ if (cpu_isar_feature(aa32_vfp_simd, env_archcpu(env))) {
/*
* SFPA is RAZ/WI from NS or if no FPU.
* FPCA is RO if NSACR.CP10 == 0, RES0 if the FPU is not present.
--
2.20.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* Re: [PATCH v2 01/17] target/arm: Add isar_feature_aa32_vfp_simd
2020-02-24 22:22 ` [PATCH v2 01/17] target/arm: Add isar_feature_aa32_vfp_simd Richard Henderson
@ 2020-02-25 13:18 ` Peter Maydell
0 siblings, 0 replies; 29+ messages in thread
From: Peter Maydell @ 2020-02-25 13:18 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-arm, QEMU Developers
On Mon, 24 Feb 2020 at 22:22, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Use this in the places that were checking ARM_FEATURE_VFP, and
> are obviously testing for the existance of the register set
> as opposed to testing for some particular instruction extension.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/arm/cpu.h | 9 +++++++++
> hw/intc/armv7m_nvic.c | 20 ++++++++++----------
> linux-user/arm/signal.c | 4 ++--
> target/arm/arch_dump.c | 11 ++++++-----
> target/arm/cpu.c | 4 ++--
> target/arm/helper.c | 4 ++--
> target/arm/m_helper.c | 11 ++++++-----
> 7 files changed, 37 insertions(+), 26 deletions(-)
>
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index 79db169e04..8841cc7fde 100644
> --- a/target/arm/helper.c
> +++ b/target/arm/helper.c
> @@ -894,7 +894,7 @@ static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri,
> * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP.
> * TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell.
> */
> - if (arm_feature(env, ARM_FEATURE_VFP)) {
> + if (cpu_isar_feature(aa32_vfp_simd, env_archcpu(env))) {
> /* VFP coprocessor: cp10 & cp11 [23:20] */
> mask |= (1 << 31) | (1 << 30) | (0xf << 20);
This use in cpacr_write() is ok but it prompted me to have
a look at the whole function, which is used also for AArch64
CPACR_EL1. Currently we have an odd setup where for a pre-v8
core we carefully check and enforce the RAZ/WI bits, but
for v8 we allow any random bits to be set. Anyway, that's
I guess architecturally valid and not an issue related to
this patchset, so:
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH v2 02/17] target/arm: Rename isar_feature_aa32_fpdp_v2
2020-02-24 22:22 [PATCH v2 00/17] target/arm: vfp feature and decodetree cleanup Richard Henderson
2020-02-24 22:22 ` [PATCH v2 01/17] target/arm: Add isar_feature_aa32_vfp_simd Richard Henderson
@ 2020-02-24 22:22 ` Richard Henderson
2020-02-24 22:22 ` [PATCH v2 03/17] target/arm: Add isar_feature_aa32_{fpsp_v2, fpsp_v3, fpdp_v3} Richard Henderson
` (15 subsequent siblings)
17 siblings, 0 replies; 29+ messages in thread
From: Richard Henderson @ 2020-02-24 22:22 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, qemu-arm, Philippe Mathieu-Daudé
The old name, isar_feature_aa32_fpdp, does not reflect
that the test includes VFPv2. We will introduce another
feature tests for VFPv3.
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/cpu.h | 4 ++--
target/arm/translate-vfp.inc.c | 40 +++++++++++++++++-----------------
2 files changed, 22 insertions(+), 22 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index a128d48d40..1e6eac0cd2 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3470,9 +3470,9 @@ static inline bool isar_feature_aa32_fpshvec(const ARMISARegisters *id)
return FIELD_EX32(id->mvfr0, MVFR0, FPSHVEC) > 0;
}
-static inline bool isar_feature_aa32_fpdp(const ARMISARegisters *id)
+static inline bool isar_feature_aa32_fpdp_v2(const ARMISARegisters *id)
{
- /* Return true if CPU supports double precision floating point */
+ /* Return true if CPU supports double precision floating point, VFPv2 */
return FIELD_EX32(id->mvfr0, MVFR0, FPDP) > 0;
}
diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c
index ba46e2557a..e94876c30c 100644
--- a/target/arm/translate-vfp.inc.c
+++ b/target/arm/translate-vfp.inc.c
@@ -206,7 +206,7 @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a)
return false;
}
- if (dp && !dc_isar_feature(aa32_fpdp, s)) {
+ if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
@@ -339,7 +339,7 @@ static bool trans_VMINMAXNM(DisasContext *s, arg_VMINMAXNM *a)
return false;
}
- if (dp && !dc_isar_feature(aa32_fpdp, s)) {
+ if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
@@ -425,7 +425,7 @@ static bool trans_VRINT(DisasContext *s, arg_VRINT *a)
return false;
}
- if (dp && !dc_isar_feature(aa32_fpdp, s)) {
+ if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
@@ -488,7 +488,7 @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a)
return false;
}
- if (dp && !dc_isar_feature(aa32_fpdp, s)) {
+ if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
@@ -1313,7 +1313,7 @@ static bool do_vfp_3op_dp(DisasContext *s, VFPGen3OpDPFn *fn,
return false;
}
- if (!dc_isar_feature(aa32_fpdp, s)) {
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
@@ -1462,7 +1462,7 @@ static bool do_vfp_2op_dp(DisasContext *s, VFPGen2OpDPFn *fn, int vd, int vm)
return false;
}
- if (!dc_isar_feature(aa32_fpdp, s)) {
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
@@ -1827,7 +1827,7 @@ static bool trans_VFM_dp(DisasContext *s, arg_VFM_dp *a)
return false;
}
- if (!dc_isar_feature(aa32_fpdp, s)) {
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
@@ -1926,7 +1926,7 @@ static bool trans_VMOV_imm_dp(DisasContext *s, arg_VMOV_imm_dp *a)
return false;
}
- if (!dc_isar_feature(aa32_fpdp, s)) {
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
@@ -2070,7 +2070,7 @@ static bool trans_VCMP_dp(DisasContext *s, arg_VCMP_dp *a)
return false;
}
- if (!dc_isar_feature(aa32_fpdp, s)) {
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
@@ -2143,7 +2143,7 @@ static bool trans_VCVT_f64_f16(DisasContext *s, arg_VCVT_f64_f16 *a)
return false;
}
- if (!dc_isar_feature(aa32_fpdp, s)) {
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
@@ -2209,7 +2209,7 @@ static bool trans_VCVT_f16_f64(DisasContext *s, arg_VCVT_f16_f64 *a)
return false;
}
- if (!dc_isar_feature(aa32_fpdp, s)) {
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
@@ -2269,7 +2269,7 @@ static bool trans_VRINTR_dp(DisasContext *s, arg_VRINTR_dp *a)
return false;
}
- if (!dc_isar_feature(aa32_fpdp, s)) {
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
@@ -2330,7 +2330,7 @@ static bool trans_VRINTZ_dp(DisasContext *s, arg_VRINTZ_dp *a)
return false;
}
- if (!dc_isar_feature(aa32_fpdp, s)) {
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
@@ -2389,7 +2389,7 @@ static bool trans_VRINTX_dp(DisasContext *s, arg_VRINTX_dp *a)
return false;
}
- if (!dc_isar_feature(aa32_fpdp, s)) {
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
@@ -2417,7 +2417,7 @@ static bool trans_VCVT_sp(DisasContext *s, arg_VCVT_sp *a)
return false;
}
- if (!dc_isar_feature(aa32_fpdp, s)) {
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
@@ -2445,7 +2445,7 @@ static bool trans_VCVT_dp(DisasContext *s, arg_VCVT_dp *a)
return false;
}
- if (!dc_isar_feature(aa32_fpdp, s)) {
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
@@ -2499,7 +2499,7 @@ static bool trans_VCVT_int_dp(DisasContext *s, arg_VCVT_int_dp *a)
return false;
}
- if (!dc_isar_feature(aa32_fpdp, s)) {
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
@@ -2539,7 +2539,7 @@ static bool trans_VJCVT(DisasContext *s, arg_VJCVT *a)
return false;
}
- if (!dc_isar_feature(aa32_fpdp, s)) {
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
@@ -2632,7 +2632,7 @@ static bool trans_VCVT_fix_dp(DisasContext *s, arg_VCVT_fix_dp *a)
return false;
}
- if (!dc_isar_feature(aa32_fpdp, s)) {
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
@@ -2728,7 +2728,7 @@ static bool trans_VCVT_dp_int(DisasContext *s, arg_VCVT_dp_int *a)
return false;
}
- if (!dc_isar_feature(aa32_fpdp, s)) {
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
--
2.20.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH v2 03/17] target/arm: Add isar_feature_aa32_{fpsp_v2, fpsp_v3, fpdp_v3}
2020-02-24 22:22 [PATCH v2 00/17] target/arm: vfp feature and decodetree cleanup Richard Henderson
2020-02-24 22:22 ` [PATCH v2 01/17] target/arm: Add isar_feature_aa32_vfp_simd Richard Henderson
2020-02-24 22:22 ` [PATCH v2 02/17] target/arm: Rename isar_feature_aa32_fpdp_v2 Richard Henderson
@ 2020-02-24 22:22 ` Richard Henderson
2020-02-24 22:22 ` [PATCH v2 04/17] target/arm: Add isar_feature_aa64_fp_simd, isar_feature_aa32_vfp Richard Henderson
` (14 subsequent siblings)
17 siblings, 0 replies; 29+ messages in thread
From: Richard Henderson @ 2020-02-24 22:22 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, qemu-arm
We will shortly use these to test for VFPv2 and VFPv3
in different situations.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/cpu.h | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 1e6eac0cd2..f7a90f512e 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3470,12 +3470,30 @@ static inline bool isar_feature_aa32_fpshvec(const ARMISARegisters *id)
return FIELD_EX32(id->mvfr0, MVFR0, FPSHVEC) > 0;
}
+static inline bool isar_feature_aa32_fpsp_v2(const ARMISARegisters *id)
+{
+ /* Return true if CPU supports single precision floating point, VFPv2 */
+ return FIELD_EX32(id->mvfr0, MVFR0, FPSP) > 0;
+}
+
+static inline bool isar_feature_aa32_fpsp_v3(const ARMISARegisters *id)
+{
+ /* Return true if CPU supports single precision floating point, VFPv3 */
+ return FIELD_EX32(id->mvfr0, MVFR0, FPSP) >= 2;
+}
+
static inline bool isar_feature_aa32_fpdp_v2(const ARMISARegisters *id)
{
/* Return true if CPU supports double precision floating point, VFPv2 */
return FIELD_EX32(id->mvfr0, MVFR0, FPDP) > 0;
}
+static inline bool isar_feature_aa32_fpdp_v3(const ARMISARegisters *id)
+{
+ /* Return true if CPU supports double precision floating point, VFPv3 */
+ return FIELD_EX32(id->mvfr0, MVFR0, FPDP) >= 2;
+}
+
/*
* We always set the FP and SIMD FP16 fields to indicate identical
* levels of support (assuming SIMD is implemented at all), so
--
2.20.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH v2 04/17] target/arm: Add isar_feature_aa64_fp_simd, isar_feature_aa32_vfp
2020-02-24 22:22 [PATCH v2 00/17] target/arm: vfp feature and decodetree cleanup Richard Henderson
` (2 preceding siblings ...)
2020-02-24 22:22 ` [PATCH v2 03/17] target/arm: Add isar_feature_aa32_{fpsp_v2, fpsp_v3, fpdp_v3} Richard Henderson
@ 2020-02-24 22:22 ` Richard Henderson
2020-02-25 13:20 ` Peter Maydell
2020-02-24 22:22 ` [PATCH v2 05/17] target/arm: Improve ID_AA64PFR0 FP/SIMD validation Richard Henderson
` (13 subsequent siblings)
17 siblings, 1 reply; 29+ messages in thread
From: Richard Henderson @ 2020-02-24 22:22 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, qemu-arm
We cannot easily create "any" functions for these, because the
ID_AA64PFR0 fields for FP and SIMD signal "enabled" with zero.
Which means that an aarch32-only cpu will return incorrect results
when testing the aarch64 registers.
To use these, we must either have context or additionally test
vs ARM_FEATURE_AARCH64.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/cpu.h | 11 +++++++++++
target/arm/cpu.c | 9 ++++++---
target/arm/machine.c | 5 +++--
3 files changed, 20 insertions(+), 5 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index f7a90f512e..b94d2a5ace 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3494,6 +3494,11 @@ static inline bool isar_feature_aa32_fpdp_v3(const ARMISARegisters *id)
return FIELD_EX32(id->mvfr0, MVFR0, FPDP) >= 2;
}
+static inline bool isar_feature_aa32_vfp(const ARMISARegisters *id)
+{
+ return isar_feature_aa32_fpsp_v2(id) || isar_feature_aa32_fpdp_v2(id);
+}
+
/*
* We always set the FP and SIMD FP16 fields to indicate identical
* levels of support (assuming SIMD is implemented at all), so
@@ -3696,6 +3701,12 @@ static inline bool isar_feature_aa64_dcpodp(const ARMISARegisters *id)
return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) >= 2;
}
+static inline bool isar_feature_aa64_fp_simd(const ARMISARegisters *id)
+{
+ /* We always set the AdvSIMD and FP fields identically. */
+ return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) != 0xf;
+}
+
static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id)
{
/* We always set the AdvSIMD and FP fields identically wrt FP16. */
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index be4c2a1253..5be4c25809 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1260,7 +1260,9 @@ void arm_cpu_post_init(Object *obj)
* KVM does not currently allow us to lie to the guest about its
* ID/feature registers, so the guest always sees what the host has.
*/
- if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) {
+ if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)
+ ? cpu_isar_feature(aa64_fp_simd, cpu)
+ : cpu_isar_feature(aa32_vfp, cpu)) {
cpu->has_vfp = true;
if (!kvm_enabled()) {
qdev_property_add_static(DEVICE(obj), &arm_cpu_has_vfp_property);
@@ -1636,8 +1638,9 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
* We rely on no XScale CPU having VFP so we can use the same bits in the
* TB flags field for VECSTRIDE and XSCALE_CPAR.
*/
- assert(!(arm_feature(env, ARM_FEATURE_VFP) &&
- arm_feature(env, ARM_FEATURE_XSCALE)));
+ assert(arm_feature(&cpu->env, ARM_FEATURE_AARCH64) ||
+ !cpu_isar_feature(aa32_vfp_simd, cpu) ||
+ !arm_feature(env, ARM_FEATURE_XSCALE));
if (arm_feature(env, ARM_FEATURE_V7) &&
!arm_feature(env, ARM_FEATURE_M) &&
diff --git a/target/arm/machine.c b/target/arm/machine.c
index 241890ac8c..c5a2114f51 100644
--- a/target/arm/machine.c
+++ b/target/arm/machine.c
@@ -9,9 +9,10 @@
static bool vfp_needed(void *opaque)
{
ARMCPU *cpu = opaque;
- CPUARMState *env = &cpu->env;
- return arm_feature(env, ARM_FEATURE_VFP);
+ return (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)
+ ? cpu_isar_feature(aa64_fp_simd, cpu)
+ : cpu_isar_feature(aa32_vfp_simd, cpu));
}
static int get_fpscr(QEMUFile *f, void *opaque, size_t size,
--
2.20.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* Re: [PATCH v2 04/17] target/arm: Add isar_feature_aa64_fp_simd, isar_feature_aa32_vfp
2020-02-24 22:22 ` [PATCH v2 04/17] target/arm: Add isar_feature_aa64_fp_simd, isar_feature_aa32_vfp Richard Henderson
@ 2020-02-25 13:20 ` Peter Maydell
0 siblings, 0 replies; 29+ messages in thread
From: Peter Maydell @ 2020-02-25 13:20 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-arm, QEMU Developers
On Mon, 24 Feb 2020 at 22:22, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> We cannot easily create "any" functions for these, because the
> ID_AA64PFR0 fields for FP and SIMD signal "enabled" with zero.
> Which means that an aarch32-only cpu will return incorrect results
> when testing the aarch64 registers.
>
> To use these, we must either have context or additionally test
> vs ARM_FEATURE_AARCH64.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/arm/cpu.h | 11 +++++++++++
> target/arm/cpu.c | 9 ++++++---
> target/arm/machine.c | 5 +++--
> 3 files changed, 20 insertions(+), 5 deletions(-)
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH v2 05/17] target/arm: Improve ID_AA64PFR0 FP/SIMD validation
2020-02-24 22:22 [PATCH v2 00/17] target/arm: vfp feature and decodetree cleanup Richard Henderson
` (3 preceding siblings ...)
2020-02-24 22:22 ` [PATCH v2 04/17] target/arm: Add isar_feature_aa64_fp_simd, isar_feature_aa32_vfp Richard Henderson
@ 2020-02-24 22:22 ` Richard Henderson
2020-02-25 13:24 ` Peter Maydell
2020-02-24 22:22 ` [PATCH v2 06/17] target/arm: Perform fpdp_v2 check first Richard Henderson
` (12 subsequent siblings)
17 siblings, 1 reply; 29+ messages in thread
From: Richard Henderson @ 2020-02-24 22:22 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, qemu-arm
When sanity checking id_aa64pfr0, use the raw FP and SIMD fields,
because the values must match. Delay the test until we've finished
modifying the id_aa64pfr0 register.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/cpu.c | 23 ++++++++++++-----------
1 file changed, 12 insertions(+), 11 deletions(-)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 5be4c25809..f10f34b655 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1427,17 +1427,6 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
return;
}
- if (arm_feature(env, ARM_FEATURE_AARCH64) &&
- cpu->has_vfp != cpu->has_neon) {
- /*
- * This is an architectural requirement for AArch64; AArch32 is
- * more flexible and permits VFP-no-Neon and Neon-no-VFP.
- */
- error_setg(errp,
- "AArch64 CPUs must have both VFP and Neon or neither");
- return;
- }
-
if (!cpu->has_vfp) {
uint64_t t;
uint32_t u;
@@ -1537,6 +1526,18 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
cpu->isar.mvfr0 = u;
}
+ if (arm_feature(env, ARM_FEATURE_AARCH64) &&
+ FIELD_EX64(cpu->isar.id_aa64pfr0, ID_AA64PFR0, FP) !=
+ FIELD_EX64(cpu->isar.id_aa64pfr0, ID_AA64PFR0, ADVSIMD)) {
+ /*
+ * This is an architectural requirement for AArch64. Not only
+ * both vfp and advsimd or neither, but further both must
+ * support fp16 or neither.
+ */
+ error_setg(errp, "AArch64 CPUs must match VFP and NEON");
+ return;
+ }
+
if (arm_feature(env, ARM_FEATURE_M) && !cpu->has_dsp) {
uint32_t u;
--
2.20.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* Re: [PATCH v2 05/17] target/arm: Improve ID_AA64PFR0 FP/SIMD validation
2020-02-24 22:22 ` [PATCH v2 05/17] target/arm: Improve ID_AA64PFR0 FP/SIMD validation Richard Henderson
@ 2020-02-25 13:24 ` Peter Maydell
2020-02-25 15:55 ` Richard Henderson
0 siblings, 1 reply; 29+ messages in thread
From: Peter Maydell @ 2020-02-25 13:24 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-arm, QEMU Developers
On Mon, 24 Feb 2020 at 22:22, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> When sanity checking id_aa64pfr0, use the raw FP and SIMD fields,
> because the values must match. Delay the test until we've finished
> modifying the id_aa64pfr0 register.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/arm/cpu.c | 23 ++++++++++++-----------
> 1 file changed, 12 insertions(+), 11 deletions(-)
>
> diff --git a/target/arm/cpu.c b/target/arm/cpu.c
> index 5be4c25809..f10f34b655 100644
> --- a/target/arm/cpu.c
> +++ b/target/arm/cpu.c
> @@ -1427,17 +1427,6 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
> return;
> }
>
> - if (arm_feature(env, ARM_FEATURE_AARCH64) &&
> - cpu->has_vfp != cpu->has_neon) {
> - /*
> - * This is an architectural requirement for AArch64; AArch32 is
> - * more flexible and permits VFP-no-Neon and Neon-no-VFP.
> - */
> - error_setg(errp,
> - "AArch64 CPUs must have both VFP and Neon or neither");
> - return;
> - }
> -
> if (!cpu->has_vfp) {
> uint64_t t;
> uint32_t u;
> @@ -1537,6 +1526,18 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
> cpu->isar.mvfr0 = u;
> }
>
> + if (arm_feature(env, ARM_FEATURE_AARCH64) &&
> + FIELD_EX64(cpu->isar.id_aa64pfr0, ID_AA64PFR0, FP) !=
> + FIELD_EX64(cpu->isar.id_aa64pfr0, ID_AA64PFR0, ADVSIMD)) {
> + /*
> + * This is an architectural requirement for AArch64. Not only
> + * both vfp and advsimd or neither, but further both must
> + * support fp16 or neither.
> + */
> + error_setg(errp, "AArch64 CPUs must match VFP and NEON");
> + return;
> + }
> +
> if (arm_feature(env, ARM_FEATURE_M) && !cpu->has_dsp) {
> uint32_t u;
This check is supposed to be "did the user accidentally specify
some incompatible settings on their '-cpu,+this,-that' option?".
By making it check the actual ID register values, you're turning
it into also a check on "does the implementation specify sane
ID register values", which (a) is useful for TCG but ought to
be an assert and (b) we shouldn't be checking for KVM in case
the h/w is giving us dubious ID values.
thanks
-- PMM
^ permalink raw reply [flat|nested] 29+ messages in thread* Re: [PATCH v2 05/17] target/arm: Improve ID_AA64PFR0 FP/SIMD validation
2020-02-25 13:24 ` Peter Maydell
@ 2020-02-25 15:55 ` Richard Henderson
2020-02-25 15:58 ` Peter Maydell
0 siblings, 1 reply; 29+ messages in thread
From: Richard Henderson @ 2020-02-25 15:55 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-arm, QEMU Developers
On 2/25/20 5:24 AM, Peter Maydell wrote:
> This check is supposed to be "did the user accidentally specify
> some incompatible settings on their '-cpu,+this,-that' option?".
> By making it check the actual ID register values, you're turning
> it into also a check on "does the implementation specify sane
> ID register values", which (a) is useful for TCG but ought to
> be an assert and (b) we shouldn't be checking for KVM in case
> the h/w is giving us dubious ID values.
Hmm. Because kvm64 unconditionally set VFP and NEON, you're right. It was
only kvm32 that was examining id registers.
The only consequence of kvm giving us dubious id values that I can see is if
ADVSIMD is on, but FP is off, we won't migrate the register set.
Do you want me to add a tcg_enabled check, or shall we just drop the patch?
The existing test is good enough for just checking the command-line.
r~
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH v2 05/17] target/arm: Improve ID_AA64PFR0 FP/SIMD validation
2020-02-25 15:55 ` Richard Henderson
@ 2020-02-25 15:58 ` Peter Maydell
2020-02-25 16:00 ` Richard Henderson
0 siblings, 1 reply; 29+ messages in thread
From: Peter Maydell @ 2020-02-25 15:58 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-arm, QEMU Developers
On Tue, 25 Feb 2020 at 15:55, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> On 2/25/20 5:24 AM, Peter Maydell wrote:
> > This check is supposed to be "did the user accidentally specify
> > some incompatible settings on their '-cpu,+this,-that' option?".
> > By making it check the actual ID register values, you're turning
> > it into also a check on "does the implementation specify sane
> > ID register values", which (a) is useful for TCG but ought to
> > be an assert and (b) we shouldn't be checking for KVM in case
> > the h/w is giving us dubious ID values.
>
> Hmm. Because kvm64 unconditionally set VFP and NEON, you're right. It was
> only kvm32 that was examining id registers.
>
> The only consequence of kvm giving us dubious id values that I can see is if
> ADVSIMD is on, but FP is off, we won't migrate the register set.
>
> Do you want me to add a tcg_enabled check, or shall we just drop the patch?
> The existing test is good enough for just checking the command-line.
If it isn't a requirement for the rest of the series, let's just
drop the patch.
thanks
-- PMM
^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH v2 06/17] target/arm: Perform fpdp_v2 check first
2020-02-24 22:22 [PATCH v2 00/17] target/arm: vfp feature and decodetree cleanup Richard Henderson
` (4 preceding siblings ...)
2020-02-24 22:22 ` [PATCH v2 05/17] target/arm: Improve ID_AA64PFR0 FP/SIMD validation Richard Henderson
@ 2020-02-24 22:22 ` Richard Henderson
2020-02-24 22:22 ` [PATCH v2 07/17] target/arm: Replace ARM_FEATURE_VFP3 checks with fp{sp, dp}_v3 Richard Henderson
` (11 subsequent siblings)
17 siblings, 0 replies; 29+ messages in thread
From: Richard Henderson @ 2020-02-24 22:22 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, qemu-arm
Shuffle the order of the checks so that we test the ISA
before we test anything else, such as the register arguments.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate-vfp.inc.c | 140 +++++++++++++++++----------------
1 file changed, 71 insertions(+), 69 deletions(-)
diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c
index e94876c30c..ff30165045 100644
--- a/target/arm/translate-vfp.inc.c
+++ b/target/arm/translate-vfp.inc.c
@@ -200,13 +200,13 @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a)
return false;
}
- /* UNDEF accesses to D16-D31 if they don't exist */
- if (dp && !dc_isar_feature(aa32_simd_r32, s) &&
- ((a->vm | a->vn | a->vd) & 0x10)) {
+ if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
- if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
+ /* UNDEF accesses to D16-D31 if they don't exist */
+ if (dp && !dc_isar_feature(aa32_simd_r32, s) &&
+ ((a->vm | a->vn | a->vd) & 0x10)) {
return false;
}
@@ -333,13 +333,13 @@ static bool trans_VMINMAXNM(DisasContext *s, arg_VMINMAXNM *a)
return false;
}
- /* UNDEF accesses to D16-D31 if they don't exist */
- if (dp && !dc_isar_feature(aa32_simd_r32, s) &&
- ((a->vm | a->vn | a->vd) & 0x10)) {
+ if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
- if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
+ /* UNDEF accesses to D16-D31 if they don't exist */
+ if (dp && !dc_isar_feature(aa32_simd_r32, s) &&
+ ((a->vm | a->vn | a->vd) & 0x10)) {
return false;
}
@@ -419,13 +419,13 @@ static bool trans_VRINT(DisasContext *s, arg_VRINT *a)
return false;
}
- /* UNDEF accesses to D16-D31 if they don't exist */
- if (dp && !dc_isar_feature(aa32_simd_r32, s) &&
- ((a->vm | a->vd) & 0x10)) {
+ if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
- if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
+ /* UNDEF accesses to D16-D31 if they don't exist */
+ if (dp && !dc_isar_feature(aa32_simd_r32, s) &&
+ ((a->vm | a->vd) & 0x10)) {
return false;
}
@@ -483,12 +483,12 @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a)
return false;
}
- /* UNDEF accesses to D16-D31 if they don't exist */
- if (dp && !dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) {
+ if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
- if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
+ /* UNDEF accesses to D16-D31 if they don't exist */
+ if (dp && !dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) {
return false;
}
@@ -1308,12 +1308,12 @@ static bool do_vfp_3op_dp(DisasContext *s, VFPGen3OpDPFn *fn,
TCGv_i64 f0, f1, fd;
TCGv_ptr fpst;
- /* UNDEF accesses to D16-D31 if they don't exist */
- if (!dc_isar_feature(aa32_simd_r32, s) && ((vd | vn | vm) & 0x10)) {
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
- if (!dc_isar_feature(aa32_fpdp_v2, s)) {
+ /* UNDEF accesses to D16-D31 if they don't exist */
+ if (!dc_isar_feature(aa32_simd_r32, s) && ((vd | vn | vm) & 0x10)) {
return false;
}
@@ -1457,12 +1457,12 @@ static bool do_vfp_2op_dp(DisasContext *s, VFPGen2OpDPFn *fn, int vd, int vm)
int veclen = s->vec_len;
TCGv_i64 f0, fd;
- /* UNDEF accesses to D16-D31 if they don't exist */
- if (!dc_isar_feature(aa32_simd_r32, s) && ((vd | vm) & 0x10)) {
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
- if (!dc_isar_feature(aa32_fpdp_v2, s)) {
+ /* UNDEF accesses to D16-D31 if they don't exist */
+ if (!dc_isar_feature(aa32_simd_r32, s) && ((vd | vm) & 0x10)) {
return false;
}
@@ -1827,7 +1827,9 @@ static bool trans_VFM_dp(DisasContext *s, arg_VFM_dp *a)
return false;
}
- if (!dc_isar_feature(aa32_fpdp_v2, s)) {
+ /* UNDEF accesses to D16-D31 if they don't exist. */
+ if (!dc_isar_feature(aa32_simd_r32, s) &&
+ ((a->vd | a->vn | a->vm) & 0x10)) {
return false;
}
@@ -1921,12 +1923,12 @@ static bool trans_VMOV_imm_dp(DisasContext *s, arg_VMOV_imm_dp *a)
vd = a->vd;
- /* UNDEF accesses to D16-D31 if they don't exist. */
- if (!dc_isar_feature(aa32_simd_r32, s) && (vd & 0x10)) {
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
- if (!dc_isar_feature(aa32_fpdp_v2, s)) {
+ /* UNDEF accesses to D16-D31 if they don't exist. */
+ if (!dc_isar_feature(aa32_simd_r32, s) && (vd & 0x10)) {
return false;
}
@@ -2060,6 +2062,10 @@ static bool trans_VCMP_dp(DisasContext *s, arg_VCMP_dp *a)
{
TCGv_i64 vd, vm;
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
+ return false;
+ }
+
/* Vm/M bits must be zero for the Z variant */
if (a->z && a->vm != 0) {
return false;
@@ -2070,10 +2076,6 @@ static bool trans_VCMP_dp(DisasContext *s, arg_VCMP_dp *a)
return false;
}
- if (!dc_isar_feature(aa32_fpdp_v2, s)) {
- return false;
- }
-
if (!vfp_access_check(s)) {
return true;
}
@@ -2134,6 +2136,10 @@ static bool trans_VCVT_f64_f16(DisasContext *s, arg_VCVT_f64_f16 *a)
TCGv_i32 tmp;
TCGv_i64 vd;
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
+ return false;
+ }
+
if (!dc_isar_feature(aa32_fp16_dpconv, s)) {
return false;
}
@@ -2143,10 +2149,6 @@ static bool trans_VCVT_f64_f16(DisasContext *s, arg_VCVT_f64_f16 *a)
return false;
}
- if (!dc_isar_feature(aa32_fpdp_v2, s)) {
- return false;
- }
-
if (!vfp_access_check(s)) {
return true;
}
@@ -2200,6 +2202,10 @@ static bool trans_VCVT_f16_f64(DisasContext *s, arg_VCVT_f16_f64 *a)
TCGv_i32 tmp;
TCGv_i64 vm;
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
+ return false;
+ }
+
if (!dc_isar_feature(aa32_fp16_dpconv, s)) {
return false;
}
@@ -2209,10 +2215,6 @@ static bool trans_VCVT_f16_f64(DisasContext *s, arg_VCVT_f16_f64 *a)
return false;
}
- if (!dc_isar_feature(aa32_fpdp_v2, s)) {
- return false;
- }
-
if (!vfp_access_check(s)) {
return true;
}
@@ -2260,6 +2262,10 @@ static bool trans_VRINTR_dp(DisasContext *s, arg_VRINTR_dp *a)
TCGv_ptr fpst;
TCGv_i64 tmp;
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
+ return false;
+ }
+
if (!dc_isar_feature(aa32_vrint, s)) {
return false;
}
@@ -2269,10 +2275,6 @@ static bool trans_VRINTR_dp(DisasContext *s, arg_VRINTR_dp *a)
return false;
}
- if (!dc_isar_feature(aa32_fpdp_v2, s)) {
- return false;
- }
-
if (!vfp_access_check(s)) {
return true;
}
@@ -2321,6 +2323,10 @@ static bool trans_VRINTZ_dp(DisasContext *s, arg_VRINTZ_dp *a)
TCGv_i64 tmp;
TCGv_i32 tcg_rmode;
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
+ return false;
+ }
+
if (!dc_isar_feature(aa32_vrint, s)) {
return false;
}
@@ -2330,10 +2336,6 @@ static bool trans_VRINTZ_dp(DisasContext *s, arg_VRINTZ_dp *a)
return false;
}
- if (!dc_isar_feature(aa32_fpdp_v2, s)) {
- return false;
- }
-
if (!vfp_access_check(s)) {
return true;
}
@@ -2380,6 +2382,10 @@ static bool trans_VRINTX_dp(DisasContext *s, arg_VRINTX_dp *a)
TCGv_ptr fpst;
TCGv_i64 tmp;
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
+ return false;
+ }
+
if (!dc_isar_feature(aa32_vrint, s)) {
return false;
}
@@ -2389,10 +2395,6 @@ static bool trans_VRINTX_dp(DisasContext *s, arg_VRINTX_dp *a)
return false;
}
- if (!dc_isar_feature(aa32_fpdp_v2, s)) {
- return false;
- }
-
if (!vfp_access_check(s)) {
return true;
}
@@ -2412,12 +2414,12 @@ static bool trans_VCVT_sp(DisasContext *s, arg_VCVT_sp *a)
TCGv_i64 vd;
TCGv_i32 vm;
- /* UNDEF accesses to D16-D31 if they don't exist. */
- if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) {
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
- if (!dc_isar_feature(aa32_fpdp_v2, s)) {
+ /* UNDEF accesses to D16-D31 if they don't exist. */
+ if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) {
return false;
}
@@ -2440,12 +2442,12 @@ static bool trans_VCVT_dp(DisasContext *s, arg_VCVT_dp *a)
TCGv_i64 vm;
TCGv_i32 vd;
- /* UNDEF accesses to D16-D31 if they don't exist. */
- if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) {
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
- if (!dc_isar_feature(aa32_fpdp_v2, s)) {
+ /* UNDEF accesses to D16-D31 if they don't exist. */
+ if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) {
return false;
}
@@ -2494,12 +2496,12 @@ static bool trans_VCVT_int_dp(DisasContext *s, arg_VCVT_int_dp *a)
TCGv_i64 vd;
TCGv_ptr fpst;
- /* UNDEF accesses to D16-D31 if they don't exist. */
- if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) {
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
- if (!dc_isar_feature(aa32_fpdp_v2, s)) {
+ /* UNDEF accesses to D16-D31 if they don't exist. */
+ if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) {
return false;
}
@@ -2530,6 +2532,10 @@ static bool trans_VJCVT(DisasContext *s, arg_VJCVT *a)
TCGv_i32 vd;
TCGv_i64 vm;
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
+ return false;
+ }
+
if (!dc_isar_feature(aa32_jscvt, s)) {
return false;
}
@@ -2539,10 +2545,6 @@ static bool trans_VJCVT(DisasContext *s, arg_VJCVT *a)
return false;
}
- if (!dc_isar_feature(aa32_fpdp_v2, s)) {
- return false;
- }
-
if (!vfp_access_check(s)) {
return true;
}
@@ -2623,6 +2625,10 @@ static bool trans_VCVT_fix_dp(DisasContext *s, arg_VCVT_fix_dp *a)
TCGv_ptr fpst;
int frac_bits;
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
+ return false;
+ }
+
if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) {
return false;
}
@@ -2632,10 +2638,6 @@ static bool trans_VCVT_fix_dp(DisasContext *s, arg_VCVT_fix_dp *a)
return false;
}
- if (!dc_isar_feature(aa32_fpdp_v2, s)) {
- return false;
- }
-
if (!vfp_access_check(s)) {
return true;
}
@@ -2723,12 +2725,12 @@ static bool trans_VCVT_dp_int(DisasContext *s, arg_VCVT_dp_int *a)
TCGv_i64 vm;
TCGv_ptr fpst;
- /* UNDEF accesses to D16-D31 if they don't exist. */
- if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) {
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
- if (!dc_isar_feature(aa32_fpdp_v2, s)) {
+ /* UNDEF accesses to D16-D31 if they don't exist. */
+ if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) {
return false;
}
--
2.20.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH v2 07/17] target/arm: Replace ARM_FEATURE_VFP3 checks with fp{sp, dp}_v3
2020-02-24 22:22 [PATCH v2 00/17] target/arm: vfp feature and decodetree cleanup Richard Henderson
` (5 preceding siblings ...)
2020-02-24 22:22 ` [PATCH v2 06/17] target/arm: Perform fpdp_v2 check first Richard Henderson
@ 2020-02-24 22:22 ` Richard Henderson
2020-02-24 22:22 ` [PATCH v2 08/17] target/arm: Add missing checks for fpsp_v2 Richard Henderson
` (10 subsequent siblings)
17 siblings, 0 replies; 29+ messages in thread
From: Richard Henderson @ 2020-02-24 22:22 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, qemu-arm
Sort this check to the start of a trans_* function.
Merge this with any existing test for fpdp_v2.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate-vfp.inc.c | 24 ++++++++----------------
1 file changed, 8 insertions(+), 16 deletions(-)
diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c
index ff30165045..51d46f4302 100644
--- a/target/arm/translate-vfp.inc.c
+++ b/target/arm/translate-vfp.inc.c
@@ -717,7 +717,7 @@ static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_VMRS *a)
* VFPv2 allows access to FPSID from userspace; VFPv3 restricts
* all ID registers to privileged access only.
*/
- if (IS_USER(s) && arm_dc_feature(s, ARM_FEATURE_VFP3)) {
+ if (IS_USER(s) && dc_isar_feature(aa32_fpsp_v3, s)) {
return false;
}
ignore_vfp_enabled = true;
@@ -746,7 +746,7 @@ static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_VMRS *a)
case ARM_VFP_FPINST:
case ARM_VFP_FPINST2:
/* Not present in VFPv3 */
- if (IS_USER(s) || arm_dc_feature(s, ARM_FEATURE_VFP3)) {
+ if (IS_USER(s) || dc_isar_feature(aa32_fpsp_v3, s)) {
return false;
}
break;
@@ -1873,12 +1873,12 @@ static bool trans_VMOV_imm_sp(DisasContext *s, arg_VMOV_imm_sp *a)
vd = a->vd;
- if (!dc_isar_feature(aa32_fpshvec, s) &&
- (veclen != 0 || s->vec_stride != 0)) {
+ if (!dc_isar_feature(aa32_fpsp_v3, s)) {
return false;
}
- if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) {
+ if (!dc_isar_feature(aa32_fpshvec, s) &&
+ (veclen != 0 || s->vec_stride != 0)) {
return false;
}
@@ -1923,7 +1923,7 @@ static bool trans_VMOV_imm_dp(DisasContext *s, arg_VMOV_imm_dp *a)
vd = a->vd;
- if (!dc_isar_feature(aa32_fpdp_v2, s)) {
+ if (!dc_isar_feature(aa32_fpdp_v3, s)) {
return false;
}
@@ -1937,10 +1937,6 @@ static bool trans_VMOV_imm_dp(DisasContext *s, arg_VMOV_imm_dp *a)
return false;
}
- if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) {
- return false;
- }
-
if (!vfp_access_check(s)) {
return true;
}
@@ -2565,7 +2561,7 @@ static bool trans_VCVT_fix_sp(DisasContext *s, arg_VCVT_fix_sp *a)
TCGv_ptr fpst;
int frac_bits;
- if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) {
+ if (!dc_isar_feature(aa32_fpsp_v3, s)) {
return false;
}
@@ -2625,11 +2621,7 @@ static bool trans_VCVT_fix_dp(DisasContext *s, arg_VCVT_fix_dp *a)
TCGv_ptr fpst;
int frac_bits;
- if (!dc_isar_feature(aa32_fpdp_v2, s)) {
- return false;
- }
-
- if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) {
+ if (!dc_isar_feature(aa32_fpdp_v3, s)) {
return false;
}
--
2.20.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH v2 08/17] target/arm: Add missing checks for fpsp_v2
2020-02-24 22:22 [PATCH v2 00/17] target/arm: vfp feature and decodetree cleanup Richard Henderson
` (6 preceding siblings ...)
2020-02-24 22:22 ` [PATCH v2 07/17] target/arm: Replace ARM_FEATURE_VFP3 checks with fp{sp, dp}_v3 Richard Henderson
@ 2020-02-24 22:22 ` Richard Henderson
2020-02-24 22:22 ` [PATCH v2 09/17] target/arm: Replace ARM_FEATURE_VFP4 with isar_feature_aa32_simdfmac Richard Henderson
` (9 subsequent siblings)
17 siblings, 0 replies; 29+ messages in thread
From: Richard Henderson @ 2020-02-24 22:22 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, qemu-arm
We will eventually remove the early ARM_FEATURE_VFP test,
so add a proper test for each trans_* that does not already
have another ISA test.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate-vfp.inc.c | 78 ++++++++++++++++++++++++++++++----
1 file changed, 69 insertions(+), 9 deletions(-)
diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c
index 51d46f4302..f88a95438f 100644
--- a/target/arm/translate-vfp.inc.c
+++ b/target/arm/translate-vfp.inc.c
@@ -555,6 +555,13 @@ static bool trans_VMOV_to_gp(DisasContext *s, arg_VMOV_to_gp *a)
int pass;
uint32_t offset;
+ /* SIZE == 2 is a VFP instruction; otherwise NEON. */
+ if (a->size == 2
+ ? !dc_isar_feature(aa32_fpsp_v2, s)
+ : !arm_dc_feature(s, ARM_FEATURE_NEON)) {
+ return false;
+ }
+
/* UNDEF accesses to D16-D31 if they don't exist */
if (!dc_isar_feature(aa32_simd_r32, s) && (a->vn & 0x10)) {
return false;
@@ -564,10 +571,6 @@ static bool trans_VMOV_to_gp(DisasContext *s, arg_VMOV_to_gp *a)
pass = extract32(offset, 2, 1);
offset = extract32(offset, 0, 2) * 8;
- if (a->size != 2 && !arm_dc_feature(s, ARM_FEATURE_NEON)) {
- return false;
- }
-
if (!vfp_access_check(s)) {
return true;
}
@@ -614,6 +617,13 @@ static bool trans_VMOV_from_gp(DisasContext *s, arg_VMOV_from_gp *a)
int pass;
uint32_t offset;
+ /* SIZE == 2 is a VFP instruction; otherwise NEON. */
+ if (a->size == 2
+ ? !dc_isar_feature(aa32_fpsp_v2, s)
+ : !arm_dc_feature(s, ARM_FEATURE_NEON)) {
+ return false;
+ }
+
/* UNDEF accesses to D16-D31 if they don't exist */
if (!dc_isar_feature(aa32_simd_r32, s) && (a->vn & 0x10)) {
return false;
@@ -623,10 +633,6 @@ static bool trans_VMOV_from_gp(DisasContext *s, arg_VMOV_from_gp *a)
pass = extract32(offset, 2, 1);
offset = extract32(offset, 0, 2) * 8;
- if (a->size != 2 && !arm_dc_feature(s, ARM_FEATURE_NEON)) {
- return false;
- }
-
if (!vfp_access_check(s)) {
return true;
}
@@ -700,6 +706,10 @@ static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_VMRS *a)
TCGv_i32 tmp;
bool ignore_vfp_enabled = false;
+ if (!dc_isar_feature(aa32_fpsp_v2, s)) {
+ return false;
+ }
+
if (arm_dc_feature(s, ARM_FEATURE_M)) {
/*
* The only M-profile VFP vmrs/vmsr sysreg is FPSCR.
@@ -844,6 +854,10 @@ static bool trans_VMOV_single(DisasContext *s, arg_VMOV_single *a)
{
TCGv_i32 tmp;
+ if (!dc_isar_feature(aa32_fpsp_v2, s)) {
+ return false;
+ }
+
if (!vfp_access_check(s)) {
return true;
}
@@ -873,6 +887,10 @@ static bool trans_VMOV_64_sp(DisasContext *s, arg_VMOV_64_sp *a)
{
TCGv_i32 tmp;
+ if (!dc_isar_feature(aa32_fpsp_v2, s)) {
+ return false;
+ }
+
/*
* VMOV between two general-purpose registers and two single precision
* floating point registers
@@ -908,8 +926,12 @@ static bool trans_VMOV_64_dp(DisasContext *s, arg_VMOV_64_dp *a)
/*
* VMOV between two general-purpose registers and one double precision
- * floating point register
+ * floating point register. Note that this does not require support
+ * for double precision arithmetic.
*/
+ if (!dc_isar_feature(aa32_fpsp_v2, s)) {
+ return false;
+ }
/* UNDEF accesses to D16-D31 if they don't exist */
if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) {
@@ -946,6 +968,10 @@ static bool trans_VLDR_VSTR_sp(DisasContext *s, arg_VLDR_VSTR_sp *a)
uint32_t offset;
TCGv_i32 addr, tmp;
+ if (!dc_isar_feature(aa32_fpsp_v2, s)) {
+ return false;
+ }
+
if (!vfp_access_check(s)) {
return true;
}
@@ -977,6 +1003,11 @@ static bool trans_VLDR_VSTR_dp(DisasContext *s, arg_VLDR_VSTR_dp *a)
TCGv_i32 addr;
TCGv_i64 tmp;
+ /* Note that this does not require support for double arithmetic. */
+ if (!dc_isar_feature(aa32_fpsp_v2, s)) {
+ return false;
+ }
+
/* UNDEF accesses to D16-D31 if they don't exist */
if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) {
return false;
@@ -1013,6 +1044,10 @@ static bool trans_VLDM_VSTM_sp(DisasContext *s, arg_VLDM_VSTM_sp *a)
TCGv_i32 addr, tmp;
int i, n;
+ if (!dc_isar_feature(aa32_fpsp_v2, s)) {
+ return false;
+ }
+
n = a->imm;
if (n == 0 || (a->vd + n) > 32) {
@@ -1086,6 +1121,11 @@ static bool trans_VLDM_VSTM_dp(DisasContext *s, arg_VLDM_VSTM_dp *a)
TCGv_i64 tmp;
int i, n;
+ /* Note that this does not require support for double arithmetic. */
+ if (!dc_isar_feature(aa32_fpsp_v2, s)) {
+ return false;
+ }
+
n = a->imm >> 1;
if (n == 0 || (a->vd + n) > 32 || n > 16) {
@@ -1234,6 +1274,10 @@ static bool do_vfp_3op_sp(DisasContext *s, VFPGen3OpSPFn *fn,
TCGv_i32 f0, f1, fd;
TCGv_ptr fpst;
+ if (!dc_isar_feature(aa32_fpsp_v2, s)) {
+ return false;
+ }
+
if (!dc_isar_feature(aa32_fpshvec, s) &&
(veclen != 0 || s->vec_stride != 0)) {
return false;
@@ -1388,6 +1432,10 @@ static bool do_vfp_2op_sp(DisasContext *s, VFPGen2OpSPFn *fn, int vd, int vm)
int veclen = s->vec_len;
TCGv_i32 f0, fd;
+ if (!dc_isar_feature(aa32_fpsp_v2, s)) {
+ return false;
+ }
+
if (!dc_isar_feature(aa32_fpshvec, s) &&
(veclen != 0 || s->vec_stride != 0)) {
return false;
@@ -2023,6 +2071,10 @@ static bool trans_VCMP_sp(DisasContext *s, arg_VCMP_sp *a)
{
TCGv_i32 vd, vm;
+ if (!dc_isar_feature(aa32_fpsp_v2, s)) {
+ return false;
+ }
+
/* Vm/M bits must be zero for the Z variant */
if (a->z && a->vm != 0) {
return false;
@@ -2466,6 +2518,10 @@ static bool trans_VCVT_int_sp(DisasContext *s, arg_VCVT_int_sp *a)
TCGv_i32 vm;
TCGv_ptr fpst;
+ if (!dc_isar_feature(aa32_fpsp_v2, s)) {
+ return false;
+ }
+
if (!vfp_access_check(s)) {
return true;
}
@@ -2684,6 +2740,10 @@ static bool trans_VCVT_sp_int(DisasContext *s, arg_VCVT_sp_int *a)
TCGv_i32 vm;
TCGv_ptr fpst;
+ if (!dc_isar_feature(aa32_fpsp_v2, s)) {
+ return false;
+ }
+
if (!vfp_access_check(s)) {
return true;
}
--
2.20.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH v2 09/17] target/arm: Replace ARM_FEATURE_VFP4 with isar_feature_aa32_simdfmac
2020-02-24 22:22 [PATCH v2 00/17] target/arm: vfp feature and decodetree cleanup Richard Henderson
` (7 preceding siblings ...)
2020-02-24 22:22 ` [PATCH v2 08/17] target/arm: Add missing checks for fpsp_v2 Richard Henderson
@ 2020-02-24 22:22 ` Richard Henderson
2020-02-25 13:25 ` Peter Maydell
2020-02-24 22:22 ` [PATCH v2 10/17] target/arm: Remove ARM_FEATURE_VFP check from disas_vfp_insn Richard Henderson
` (8 subsequent siblings)
17 siblings, 1 reply; 29+ messages in thread
From: Richard Henderson @ 2020-02-24 22:22 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, qemu-arm
All remaining tests for VFP4 are for fused multiply-add insns.
Since the MVFR1 field is used for both VFP and NEON, move its adjustment
from the !has_neon block to the (!has_vfp && !has_neon) block.
Test for vfp of the appropraite width alongside the test for simdfmac
within translate-vfp.inc.c. Within disas_neon_data_insn, we have
already tested for ARM_FEATURE_NEON.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
v2: Applied Peter's fixups, plus test fpdp_v2 in trans_VFM_dp.
---
target/arm/cpu.h | 12 ++++++++++++
target/arm/cpu.c | 6 +++++-
target/arm/translate-vfp.inc.c | 22 ++++++++++++++++++----
target/arm/translate.c | 2 +-
4 files changed, 36 insertions(+), 6 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index b94d2a5ace..b29b0eddfc 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3514,6 +3514,18 @@ static inline bool isar_feature_aa32_fp16_dpconv(const ARMISARegisters *id)
return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 1;
}
+/*
+ * Note that this ID register field covers both VFP and Neon FMAC,
+ * so should usually be tested in combination with some other
+ * check that confirms the presence of whichever of VFP or Neon is
+ * relevant, to avoid accidentally enabling a Neon feature on
+ * a VFP-no-Neon core or vice-versa.
+ */
+static inline bool isar_feature_aa32_simdfmac(const ARMISARegisters *id)
+{
+ return FIELD_EX32(id->mvfr1, MVFR1, SIMDFMAC) != 0;
+}
+
static inline bool isar_feature_aa32_vsel(const ARMISARegisters *id)
{
return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 1;
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index f10f34b655..bdcaa46b8a 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1501,7 +1501,6 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
u = FIELD_DP32(u, MVFR1, SIMDINT, 0);
u = FIELD_DP32(u, MVFR1, SIMDSP, 0);
u = FIELD_DP32(u, MVFR1, SIMDHP, 0);
- u = FIELD_DP32(u, MVFR1, SIMDFMAC, 0);
cpu->isar.mvfr1 = u;
u = cpu->isar.mvfr2;
@@ -1524,6 +1523,11 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
u = cpu->isar.mvfr0;
u = FIELD_DP32(u, MVFR0, SIMDREG, 0);
cpu->isar.mvfr0 = u;
+
+ /* Despite the name, this field covers both VFP and Neon */
+ u = cpu->isar.mvfr1;
+ u = FIELD_DP32(u, MVFR1, SIMDFMAC, 0);
+ cpu->isar.mvfr1 = u;
}
if (arm_feature(env, ARM_FEATURE_AARCH64) &&
diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c
index f88a95438f..03ba8d7aac 100644
--- a/target/arm/translate-vfp.inc.c
+++ b/target/arm/translate-vfp.inc.c
@@ -1803,11 +1803,18 @@ static bool trans_VFM_sp(DisasContext *s, arg_VFM_sp *a)
/*
* Present in VFPv4 only.
+ * Note that we can't rely on the SIMDFMAC check alone, because
+ * in a Neon-no-VFP core that ID register field will be non-zero.
+ */
+ if (!dc_isar_feature(aa32_simdfmac, s) ||
+ !dc_isar_feature(aa32_fpsp_v2, s)) {
+ return false;
+ }
+ /*
* In v7A, UNPREDICTABLE with non-zero vector length/stride; from
* v8A, must UNDEF. We choose to UNDEF for both v7A and v8A.
*/
- if (!arm_dc_feature(s, ARM_FEATURE_VFP4) ||
- (s->vec_len != 0 || s->vec_stride != 0)) {
+ if (s->vec_len != 0 || s->vec_stride != 0) {
return false;
}
@@ -1861,11 +1868,18 @@ static bool trans_VFM_dp(DisasContext *s, arg_VFM_dp *a)
/*
* Present in VFPv4 only.
+ * Note that we can't rely on the SIMDFMAC check alone, because
+ * in a Neon-no-VFP core that ID register field will be non-zero.
+ */
+ if (!dc_isar_feature(aa32_simdfmac, s) ||
+ !dc_isar_feature(aa32_fpdp_v2, s)) {
+ return false;
+ }
+ /*
* In v7A, UNPREDICTABLE with non-zero vector length/stride; from
* v8A, must UNDEF. We choose to UNDEF for both v7A and v8A.
*/
- if (!arm_dc_feature(s, ARM_FEATURE_VFP4) ||
- (s->vec_len != 0 || s->vec_stride != 0)) {
+ if (s->vec_len != 0 || s->vec_stride != 0) {
return false;
}
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 79880adaad..0489e0cdaa 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -5150,7 +5150,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
}
break;
case NEON_3R_VFM_VQRDMLSH:
- if (!arm_dc_feature(s, ARM_FEATURE_VFP4)) {
+ if (!dc_isar_feature(aa32_simdfmac, s)) {
return 1;
}
break;
--
2.20.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* Re: [PATCH v2 09/17] target/arm: Replace ARM_FEATURE_VFP4 with isar_feature_aa32_simdfmac
2020-02-24 22:22 ` [PATCH v2 09/17] target/arm: Replace ARM_FEATURE_VFP4 with isar_feature_aa32_simdfmac Richard Henderson
@ 2020-02-25 13:25 ` Peter Maydell
0 siblings, 0 replies; 29+ messages in thread
From: Peter Maydell @ 2020-02-25 13:25 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-arm, QEMU Developers
On Mon, 24 Feb 2020 at 22:22, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> All remaining tests for VFP4 are for fused multiply-add insns.
>
> Since the MVFR1 field is used for both VFP and NEON, move its adjustment
> from the !has_neon block to the (!has_vfp && !has_neon) block.
>
> Test for vfp of the appropraite width alongside the test for simdfmac
"appropriate"
> within translate-vfp.inc.c. Within disas_neon_data_insn, we have
> already tested for ARM_FEATURE_NEON.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH v2 10/17] target/arm: Remove ARM_FEATURE_VFP check from disas_vfp_insn
2020-02-24 22:22 [PATCH v2 00/17] target/arm: vfp feature and decodetree cleanup Richard Henderson
` (8 preceding siblings ...)
2020-02-24 22:22 ` [PATCH v2 09/17] target/arm: Replace ARM_FEATURE_VFP4 with isar_feature_aa32_simdfmac Richard Henderson
@ 2020-02-24 22:22 ` Richard Henderson
2020-02-24 22:22 ` [PATCH v2 11/17] target/arm: Move VLLDM and VLSTM to vfp.decode Richard Henderson
` (7 subsequent siblings)
17 siblings, 0 replies; 29+ messages in thread
From: Richard Henderson @ 2020-02-24 22:22 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, qemu-arm
We now have proper ISA checks within each trans_* function.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate.c | 4 ----
1 file changed, 4 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 0489e0cdaa..893911fca7 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -2652,10 +2652,6 @@ static void gen_neon_dup_high16(TCGv_i32 var)
*/
static int disas_vfp_insn(DisasContext *s, uint32_t insn)
{
- if (!arm_dc_feature(s, ARM_FEATURE_VFP)) {
- return 1;
- }
-
/*
* If the decodetree decoder handles this insn it will always
* emit code to either execute the insn or generate an appropriate
--
2.20.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH v2 11/17] target/arm: Move VLLDM and VLSTM to vfp.decode
2020-02-24 22:22 [PATCH v2 00/17] target/arm: vfp feature and decodetree cleanup Richard Henderson
` (9 preceding siblings ...)
2020-02-24 22:22 ` [PATCH v2 10/17] target/arm: Remove ARM_FEATURE_VFP check from disas_vfp_insn Richard Henderson
@ 2020-02-24 22:22 ` Richard Henderson
2020-02-25 13:26 ` Peter Maydell
2020-02-24 22:22 ` [PATCH v2 12/17] target/arm: Move the vfp decodetree calls next to the base isa Richard Henderson
` (6 subsequent siblings)
17 siblings, 1 reply; 29+ messages in thread
From: Richard Henderson @ 2020-02-24 22:22 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, qemu-arm
Now that we no longer have an early check for ARM_FEATURE_VFP,
we can use the proper ISA check in trans_VLLDM_VLSTM.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
v2: Fix !secure (pmm)
---
target/arm/vfp.decode | 2 ++
target/arm/translate-vfp.inc.c | 39 +++++++++++++++++++++++++
target/arm/translate.c | 53 ++++++----------------------------
3 files changed, 50 insertions(+), 44 deletions(-)
diff --git a/target/arm/vfp.decode b/target/arm/vfp.decode
index a67b3f29ee..592fe9e1e4 100644
--- a/target/arm/vfp.decode
+++ b/target/arm/vfp.decode
@@ -242,3 +242,5 @@ VCVT_sp_int ---- 1110 1.11 110 s:1 .... 1010 rz:1 1.0 .... \
vd=%vd_sp vm=%vm_sp
VCVT_dp_int ---- 1110 1.11 110 s:1 .... 1011 rz:1 1.0 .... \
vd=%vd_sp vm=%vm_dp
+
+VLLDM_VLSTM 1110 1100 001 l:1 rn:4 0000 1010 0000 0000
diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c
index 03ba8d7aac..1964af3ea5 100644
--- a/target/arm/translate-vfp.inc.c
+++ b/target/arm/translate-vfp.inc.c
@@ -2828,3 +2828,42 @@ static bool trans_VCVT_dp_int(DisasContext *s, arg_VCVT_dp_int *a)
tcg_temp_free_ptr(fpst);
return true;
}
+
+/*
+ * Decode VLLDM and VLSTM are nonstandard because:
+ * * if there is no FPU then these insns must NOP in
+ * Secure state and UNDEF in Nonsecure state
+ * * if there is an FPU then these insns do not have
+ * the usual behaviour that vfp_access_check() provides of
+ * being controlled by CPACR/NSACR enable bits or the
+ * lazy-stacking logic.
+ */
+static bool trans_VLLDM_VLSTM(DisasContext *s, arg_VLLDM_VLSTM *a)
+{
+ TCGv_i32 fptr;
+
+ if (!arm_dc_feature(s, ARM_FEATURE_M) ||
+ !arm_dc_feature(s, ARM_FEATURE_V8)) {
+ return false;
+ }
+ /* If not secure, UNDEF. */
+ if (!s->v8m_secure) {
+ return false;
+ }
+ /* If no fpu, NOP. */
+ if (!dc_isar_feature(aa32_vfp, s)) {
+ return true;
+ }
+
+ fptr = load_reg(s, a->rn);
+ if (a->l) {
+ gen_helper_v7m_vlldm(cpu_env, fptr);
+ } else {
+ gen_helper_v7m_vlstm(cpu_env, fptr);
+ }
+ tcg_temp_free_i32(fptr);
+
+ /* End the TB, because we have updated FP control bits */
+ s->base.is_jmp = DISAS_UPDATE;
+ return true;
+}
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 893911fca7..5b7cad1ea2 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -10962,53 +10962,18 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
goto illegal_op; /* op0 = 0b11 : unallocated */
}
- /*
- * Decode VLLDM and VLSTM first: these are nonstandard because:
- * * if there is no FPU then these insns must NOP in
- * Secure state and UNDEF in Nonsecure state
- * * if there is an FPU then these insns do not have
- * the usual behaviour that disas_vfp_insn() provides of
- * being controlled by CPACR/NSACR enable bits or the
- * lazy-stacking logic.
- */
- if (arm_dc_feature(s, ARM_FEATURE_V8) &&
- (insn & 0xffa00f00) == 0xec200a00) {
- /* 0b1110_1100_0x1x_xxxx_xxxx_1010_xxxx_xxxx
- * - VLLDM, VLSTM
- * We choose to UNDEF if the RAZ bits are non-zero.
- */
- if (!s->v8m_secure || (insn & 0x0040f0ff)) {
+ if (disas_vfp_insn(s, insn)) {
+ if (((insn >> 8) & 0xe) == 10 &&
+ dc_isar_feature(aa32_fpsp_v2, s)) {
+ /* FP, and the CPU supports it */
goto illegal_op;
+ } else {
+ /* All other insns: NOCP */
+ gen_exception_insn(s, s->pc_curr, EXCP_NOCP,
+ syn_uncategorized(),
+ default_exception_el(s));
}
-
- if (arm_dc_feature(s, ARM_FEATURE_VFP)) {
- uint32_t rn = (insn >> 16) & 0xf;
- TCGv_i32 fptr = load_reg(s, rn);
-
- if (extract32(insn, 20, 1)) {
- gen_helper_v7m_vlldm(cpu_env, fptr);
- } else {
- gen_helper_v7m_vlstm(cpu_env, fptr);
- }
- tcg_temp_free_i32(fptr);
-
- /* End the TB, because we have updated FP control bits */
- s->base.is_jmp = DISAS_UPDATE;
- }
- break;
}
- if (arm_dc_feature(s, ARM_FEATURE_VFP) &&
- ((insn >> 8) & 0xe) == 10) {
- /* FP, and the CPU supports it */
- if (disas_vfp_insn(s, insn)) {
- goto illegal_op;
- }
- break;
- }
-
- /* All other insns: NOCP */
- gen_exception_insn(s, s->pc_curr, EXCP_NOCP, syn_uncategorized(),
- default_exception_el(s));
break;
}
if ((insn & 0xfe000a00) == 0xfc000800
--
2.20.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* Re: [PATCH v2 11/17] target/arm: Move VLLDM and VLSTM to vfp.decode
2020-02-24 22:22 ` [PATCH v2 11/17] target/arm: Move VLLDM and VLSTM to vfp.decode Richard Henderson
@ 2020-02-25 13:26 ` Peter Maydell
0 siblings, 0 replies; 29+ messages in thread
From: Peter Maydell @ 2020-02-25 13:26 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-arm, QEMU Developers
On Mon, 24 Feb 2020 at 22:22, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Now that we no longer have an early check for ARM_FEATURE_VFP,
> we can use the proper ISA check in trans_VLLDM_VLSTM.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> v2: Fix !secure (pmm)
> ---
> target/arm/vfp.decode | 2 ++
> target/arm/translate-vfp.inc.c | 39 +++++++++++++++++++++++++
> target/arm/translate.c | 53 ++++++----------------------------
> 3 files changed, 50 insertions(+), 44 deletions(-)
>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH v2 12/17] target/arm: Move the vfp decodetree calls next to the base isa
2020-02-24 22:22 [PATCH v2 00/17] target/arm: vfp feature and decodetree cleanup Richard Henderson
` (10 preceding siblings ...)
2020-02-24 22:22 ` [PATCH v2 11/17] target/arm: Move VLLDM and VLSTM to vfp.decode Richard Henderson
@ 2020-02-24 22:22 ` Richard Henderson
2020-02-25 13:29 ` Peter Maydell
2020-02-24 22:22 ` [PATCH v2 13/17] linux-user/arm: Replace ARM_FEATURE_VFP* tests for HWCAP Richard Henderson
` (5 subsequent siblings)
17 siblings, 1 reply; 29+ messages in thread
From: Richard Henderson @ 2020-02-24 22:22 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, qemu-arm
Have the calls adjacent as an intermediate step toward
actually merging the decodes.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
v2: Fix fallthrough in disas_arm_insn vs vfp insns.
---
target/arm/translate.c | 83 +++++++++++++++---------------------------
1 file changed, 29 insertions(+), 54 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 5b7cad1ea2..6259064ea7 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -2646,31 +2646,6 @@ static void gen_neon_dup_high16(TCGv_i32 var)
tcg_temp_free_i32(tmp);
}
-/*
- * Disassemble a VFP instruction. Returns nonzero if an error occurred
- * (ie. an undefined instruction).
- */
-static int disas_vfp_insn(DisasContext *s, uint32_t insn)
-{
- /*
- * If the decodetree decoder handles this insn it will always
- * emit code to either execute the insn or generate an appropriate
- * exception; so we don't need to ever return non-zero to tell
- * the calling code to emit an UNDEF exception.
- */
- if (extract32(insn, 28, 4) == 0xf) {
- if (disas_vfp_uncond(s, insn)) {
- return 0;
- }
- } else {
- if (disas_vfp(s, insn)) {
- return 0;
- }
- }
- /* If the decodetree decoder didn't handle this insn, it must be UNDEF */
- return 1;
-}
-
static inline bool use_goto_tb(DisasContext *s, target_ulong dest)
{
#ifndef CONFIG_USER_ONLY
@@ -10778,7 +10753,9 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
ARCH(5);
/* Unconditional instructions. */
- if (disas_a32_uncond(s, insn)) {
+ /* TODO: Perhaps merge these into one decodetree output file. */
+ if (disas_a32_uncond(s, insn) ||
+ disas_vfp_uncond(s, insn)) {
return;
}
/* fall back to legacy decoder */
@@ -10805,13 +10782,6 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
}
return;
}
- if ((insn & 0x0f000e10) == 0x0e000a00) {
- /* VFP. */
- if (disas_vfp_insn(s, insn)) {
- goto illegal_op;
- }
- return;
- }
if ((insn & 0x0e000f00) == 0x0c000100) {
if (arm_dc_feature(s, ARM_FEATURE_IWMMXT)) {
/* iWMMXt register transfer. */
@@ -10842,7 +10812,9 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
arm_skip_unless(s, cond);
}
- if (disas_a32(s, insn)) {
+ /* TODO: Perhaps merge these into one decodetree output file. */
+ if (disas_a32(s, insn) ||
+ disas_vfp(s, insn)) {
return;
}
/* fall back to legacy decoder */
@@ -10852,11 +10824,10 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
case 0xd:
case 0xe:
if (((insn >> 8) & 0xe) == 10) {
- /* VFP. */
- if (disas_vfp_insn(s, insn)) {
- goto illegal_op;
- }
- } else if (disas_coproc_insn(s, insn)) {
+ /* VFP, but failed disas_vfp. */
+ goto illegal_op;
+ }
+ if (disas_coproc_insn(s, insn)) {
/* Coprocessor. */
goto illegal_op;
}
@@ -10945,7 +10916,14 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
ARCH(6T2);
}
- if (disas_t32(s, insn)) {
+ /*
+ * TODO: Perhaps merge these into one decodetree output file.
+ * Note disas_vfp is written for a32 with cond field in the
+ * top nibble. The t32 encoding requires 0xe in the top nibble.
+ */
+ if (disas_t32(s, insn) ||
+ disas_vfp_uncond(s, insn) ||
+ ((insn >> 28) == 0xe && disas_vfp(s, insn))) {
return;
}
/* fall back to legacy decoder */
@@ -10962,17 +10940,15 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
goto illegal_op; /* op0 = 0b11 : unallocated */
}
- if (disas_vfp_insn(s, insn)) {
- if (((insn >> 8) & 0xe) == 10 &&
- dc_isar_feature(aa32_fpsp_v2, s)) {
- /* FP, and the CPU supports it */
- goto illegal_op;
- } else {
- /* All other insns: NOCP */
- gen_exception_insn(s, s->pc_curr, EXCP_NOCP,
- syn_uncategorized(),
- default_exception_el(s));
- }
+ if (((insn >> 8) & 0xe) == 10 &&
+ dc_isar_feature(aa32_fpsp_v2, s)) {
+ /* FP, and the CPU supports it */
+ goto illegal_op;
+ } else {
+ /* All other insns: NOCP */
+ gen_exception_insn(s, s->pc_curr, EXCP_NOCP,
+ syn_uncategorized(),
+ default_exception_el(s));
}
break;
}
@@ -10995,9 +10971,8 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
goto illegal_op;
}
} else if (((insn >> 8) & 0xe) == 10) {
- if (disas_vfp_insn(s, insn)) {
- goto illegal_op;
- }
+ /* VFP, but failed disas_vfp. */
+ goto illegal_op;
} else {
if (insn & (1 << 28))
goto illegal_op;
--
2.20.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH v2 13/17] linux-user/arm: Replace ARM_FEATURE_VFP* tests for HWCAP
2020-02-24 22:22 [PATCH v2 00/17] target/arm: vfp feature and decodetree cleanup Richard Henderson
` (11 preceding siblings ...)
2020-02-24 22:22 ` [PATCH v2 12/17] target/arm: Move the vfp decodetree calls next to the base isa Richard Henderson
@ 2020-02-24 22:22 ` Richard Henderson
2020-02-25 13:30 ` Peter Maydell
2020-02-24 22:22 ` [PATCH v2 14/17] target/arm: Remove ARM_FEATURE_VFP* Richard Henderson
` (4 subsequent siblings)
17 siblings, 1 reply; 29+ messages in thread
From: Richard Henderson @ 2020-02-24 22:22 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, qemu-arm
Use isar feature tests instead of feature bit tests.
Although none of QEMUs current cpus have VFPv3 without D32,
replace the large comment explaining why with one line that
sets ARM_HWCAP_ARM_VFPv3D16 under the correct conditions.
Mirror the test sequence used in the linux kernel.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
v2: Use isar_feature_aa32_vfp.
---
linux-user/elfload.c | 23 +++++++++++++----------
1 file changed, 13 insertions(+), 10 deletions(-)
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
index b1a895f24c..86cda127b7 100644
--- a/linux-user/elfload.c
+++ b/linux-user/elfload.c
@@ -468,22 +468,25 @@ static uint32_t get_elf_hwcap(void)
/* EDSP is in v5TE and above, but all our v5 CPUs are v5TE */
GET_FEATURE(ARM_FEATURE_V5, ARM_HWCAP_ARM_EDSP);
- GET_FEATURE(ARM_FEATURE_VFP, ARM_HWCAP_ARM_VFP);
GET_FEATURE(ARM_FEATURE_IWMMXT, ARM_HWCAP_ARM_IWMMXT);
GET_FEATURE(ARM_FEATURE_THUMB2EE, ARM_HWCAP_ARM_THUMBEE);
GET_FEATURE(ARM_FEATURE_NEON, ARM_HWCAP_ARM_NEON);
- GET_FEATURE(ARM_FEATURE_VFP3, ARM_HWCAP_ARM_VFPv3);
GET_FEATURE(ARM_FEATURE_V6K, ARM_HWCAP_ARM_TLS);
- GET_FEATURE(ARM_FEATURE_VFP4, ARM_HWCAP_ARM_VFPv4);
+ GET_FEATURE(ARM_FEATURE_LPAE, ARM_HWCAP_ARM_LPAE);
GET_FEATURE_ID(aa32_arm_div, ARM_HWCAP_ARM_IDIVA);
GET_FEATURE_ID(aa32_thumb_div, ARM_HWCAP_ARM_IDIVT);
- /* All QEMU's VFPv3 CPUs have 32 registers, see VFP_DREG in translate.c.
- * Note that the ARM_HWCAP_ARM_VFPv3D16 bit is always the inverse of
- * ARM_HWCAP_ARM_VFPD32 (and so always clear for QEMU); it is unrelated
- * to our VFP_FP16 feature bit.
- */
- GET_FEATURE(ARM_FEATURE_VFP3, ARM_HWCAP_ARM_VFPD32);
- GET_FEATURE(ARM_FEATURE_LPAE, ARM_HWCAP_ARM_LPAE);
+ GET_FEATURE_ID(aa32_vfp, ARM_HWCAP_ARM_VFP);
+
+ if (cpu_isar_feature(aa32_fpsp_v3, cpu) ||
+ cpu_isar_feature(aa32_fpdp_v3, cpu)) {
+ hwcaps |= ARM_HWCAP_ARM_VFPv3;
+ if (cpu_isar_feature(aa32_simd_r32, cpu)) {
+ hwcaps |= ARM_HWCAP_ARM_VFPD32;
+ } else {
+ hwcaps |= ARM_HWCAP_ARM_VFPv3D16;
+ }
+ }
+ GET_FEATURE_ID(aa32_simdfmac, ARM_HWCAP_ARM_VFPv4);
return hwcaps;
}
--
2.20.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH v2 14/17] target/arm: Remove ARM_FEATURE_VFP*
2020-02-24 22:22 [PATCH v2 00/17] target/arm: vfp feature and decodetree cleanup Richard Henderson
` (12 preceding siblings ...)
2020-02-24 22:22 ` [PATCH v2 13/17] linux-user/arm: Replace ARM_FEATURE_VFP* tests for HWCAP Richard Henderson
@ 2020-02-24 22:22 ` Richard Henderson
2020-02-24 22:22 ` [PATCH v2 15/17] target/arm: Add formats for some vfp 2 and 3-register insns Richard Henderson
` (3 subsequent siblings)
17 siblings, 0 replies; 29+ messages in thread
From: Richard Henderson @ 2020-02-24 22:22 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, qemu-arm
We have converted all tests against these features
to ISAR tests.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/cpu.h | 3 ---
target/arm/cpu.c | 25 -------------------------
target/arm/cpu64.c | 3 ---
target/arm/kvm32.c | 5 -----
target/arm/kvm64.c | 1 -
5 files changed, 37 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index b29b0eddfc..05aa9711cd 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1880,7 +1880,6 @@ QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK);
* mapping in linux-user/elfload.c:get_elf_hwcap().
*/
enum arm_features {
- ARM_FEATURE_VFP,
ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */
ARM_FEATURE_XSCALE, /* Intel XScale extensions. */
ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */
@@ -1889,7 +1888,6 @@ enum arm_features {
ARM_FEATURE_V7,
ARM_FEATURE_THUMB2,
ARM_FEATURE_PMSA, /* no MMU; may have Memory Protection Unit */
- ARM_FEATURE_VFP3,
ARM_FEATURE_NEON,
ARM_FEATURE_M, /* Microcontroller profile. */
ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */
@@ -1900,7 +1898,6 @@ enum arm_features {
ARM_FEATURE_V5,
ARM_FEATURE_STRONGARM,
ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */
- ARM_FEATURE_VFP4, /* VFPv4 (implies that NEON is v2) */
ARM_FEATURE_GENERIC_TIMER,
ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */
ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index bdcaa46b8a..ebff98cb36 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1208,13 +1208,6 @@ void arm_cpu_post_init(Object *obj)
if (arm_feature(&cpu->env, ARM_FEATURE_M)) {
set_feature(&cpu->env, ARM_FEATURE_PMSA);
}
- /* Similarly for the VFP feature bits */
- if (arm_feature(&cpu->env, ARM_FEATURE_VFP4)) {
- set_feature(&cpu->env, ARM_FEATURE_VFP3);
- }
- if (arm_feature(&cpu->env, ARM_FEATURE_VFP3)) {
- set_feature(&cpu->env, ARM_FEATURE_VFP);
- }
if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) ||
arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) {
@@ -1431,10 +1424,6 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
uint64_t t;
uint32_t u;
- unset_feature(env, ARM_FEATURE_VFP);
- unset_feature(env, ARM_FEATURE_VFP3);
- unset_feature(env, ARM_FEATURE_VFP4);
-
t = cpu->isar.id_aa64isar1;
t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 0);
cpu->isar.id_aa64isar1 = t;
@@ -1866,7 +1855,6 @@ static void arm926_initfn(Object *obj)
cpu->dtb_compatible = "arm,arm926";
set_feature(&cpu->env, ARM_FEATURE_V5);
- set_feature(&cpu->env, ARM_FEATURE_VFP);
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
cpu->midr = 0x41069265;
@@ -1907,7 +1895,6 @@ static void arm1026_initfn(Object *obj)
cpu->dtb_compatible = "arm,arm1026";
set_feature(&cpu->env, ARM_FEATURE_V5);
- set_feature(&cpu->env, ARM_FEATURE_VFP);
set_feature(&cpu->env, ARM_FEATURE_AUXCR);
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
@@ -1955,7 +1942,6 @@ static void arm1136_r2_initfn(Object *obj)
cpu->dtb_compatible = "arm,arm1136";
set_feature(&cpu->env, ARM_FEATURE_V6);
- set_feature(&cpu->env, ARM_FEATURE_VFP);
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
@@ -1987,7 +1973,6 @@ static void arm1136_initfn(Object *obj)
cpu->dtb_compatible = "arm,arm1136";
set_feature(&cpu->env, ARM_FEATURE_V6K);
set_feature(&cpu->env, ARM_FEATURE_V6);
- set_feature(&cpu->env, ARM_FEATURE_VFP);
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
@@ -2018,7 +2003,6 @@ static void arm1176_initfn(Object *obj)
cpu->dtb_compatible = "arm,arm1176";
set_feature(&cpu->env, ARM_FEATURE_V6K);
- set_feature(&cpu->env, ARM_FEATURE_VFP);
set_feature(&cpu->env, ARM_FEATURE_VAPA);
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
@@ -2051,7 +2035,6 @@ static void arm11mpcore_initfn(Object *obj)
cpu->dtb_compatible = "arm,arm11mpcore";
set_feature(&cpu->env, ARM_FEATURE_V6K);
- set_feature(&cpu->env, ARM_FEATURE_VFP);
set_feature(&cpu->env, ARM_FEATURE_VAPA);
set_feature(&cpu->env, ARM_FEATURE_MPIDR);
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
@@ -2117,7 +2100,6 @@ static void cortex_m4_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_M);
set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
- set_feature(&cpu->env, ARM_FEATURE_VFP4);
cpu->midr = 0x410fc240; /* r0p0 */
cpu->pmsav7_dregion = 8;
cpu->isar.mvfr0 = 0x10110021;
@@ -2148,7 +2130,6 @@ static void cortex_m7_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_M);
set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
- set_feature(&cpu->env, ARM_FEATURE_VFP4);
cpu->midr = 0x411fc272; /* r1p2 */
cpu->pmsav7_dregion = 8;
cpu->isar.mvfr0 = 0x10110221;
@@ -2180,7 +2161,6 @@ static void cortex_m33_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
set_feature(&cpu->env, ARM_FEATURE_M_SECURITY);
set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
- set_feature(&cpu->env, ARM_FEATURE_VFP4);
cpu->midr = 0x410fd213; /* r0p3 */
cpu->pmsav7_dregion = 16;
cpu->sau_sregion = 8;
@@ -2264,7 +2244,6 @@ static void cortex_r5f_initfn(Object *obj)
ARMCPU *cpu = ARM_CPU(obj);
cortex_r5_initfn(obj);
- set_feature(&cpu->env, ARM_FEATURE_VFP3);
cpu->isar.mvfr0 = 0x10110221;
cpu->isar.mvfr1 = 0x00000011;
}
@@ -2283,7 +2262,6 @@ static void cortex_a8_initfn(Object *obj)
cpu->dtb_compatible = "arm,cortex-a8";
set_feature(&cpu->env, ARM_FEATURE_V7);
- set_feature(&cpu->env, ARM_FEATURE_VFP3);
set_feature(&cpu->env, ARM_FEATURE_NEON);
set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
@@ -2351,7 +2329,6 @@ static void cortex_a9_initfn(Object *obj)
cpu->dtb_compatible = "arm,cortex-a9";
set_feature(&cpu->env, ARM_FEATURE_V7);
- set_feature(&cpu->env, ARM_FEATURE_VFP3);
set_feature(&cpu->env, ARM_FEATURE_NEON);
set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
set_feature(&cpu->env, ARM_FEATURE_EL3);
@@ -2416,7 +2393,6 @@ static void cortex_a7_initfn(Object *obj)
cpu->dtb_compatible = "arm,cortex-a7";
set_feature(&cpu->env, ARM_FEATURE_V7VE);
- set_feature(&cpu->env, ARM_FEATURE_VFP4);
set_feature(&cpu->env, ARM_FEATURE_NEON);
set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
@@ -2462,7 +2438,6 @@ static void cortex_a15_initfn(Object *obj)
cpu->dtb_compatible = "arm,cortex-a15";
set_feature(&cpu->env, ARM_FEATURE_V7VE);
- set_feature(&cpu->env, ARM_FEATURE_VFP4);
set_feature(&cpu->env, ARM_FEATURE_NEON);
set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 0929401a4d..5cda580231 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -102,7 +102,6 @@ static void aarch64_a57_initfn(Object *obj)
cpu->dtb_compatible = "arm,cortex-a57";
set_feature(&cpu->env, ARM_FEATURE_V8);
- set_feature(&cpu->env, ARM_FEATURE_VFP4);
set_feature(&cpu->env, ARM_FEATURE_NEON);
set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
set_feature(&cpu->env, ARM_FEATURE_AARCH64);
@@ -156,7 +155,6 @@ static void aarch64_a53_initfn(Object *obj)
cpu->dtb_compatible = "arm,cortex-a53";
set_feature(&cpu->env, ARM_FEATURE_V8);
- set_feature(&cpu->env, ARM_FEATURE_VFP4);
set_feature(&cpu->env, ARM_FEATURE_NEON);
set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
set_feature(&cpu->env, ARM_FEATURE_AARCH64);
@@ -210,7 +208,6 @@ static void aarch64_a72_initfn(Object *obj)
cpu->dtb_compatible = "arm,cortex-a72";
set_feature(&cpu->env, ARM_FEATURE_V8);
- set_feature(&cpu->env, ARM_FEATURE_VFP4);
set_feature(&cpu->env, ARM_FEATURE_NEON);
set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
set_feature(&cpu->env, ARM_FEATURE_AARCH64);
diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c
index 7981ae3bc4..f703c4fcad 100644
--- a/target/arm/kvm32.c
+++ b/target/arm/kvm32.c
@@ -147,7 +147,6 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
* bits, but a few must be tested.
*/
set_feature(&features, ARM_FEATURE_V7VE);
- set_feature(&features, ARM_FEATURE_VFP3);
set_feature(&features, ARM_FEATURE_GENERIC_TIMER);
if (extract32(id_pfr0, 12, 4) == 1) {
@@ -156,10 +155,6 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
if (extract32(ahcf->isar.mvfr1, 12, 4) == 1) {
set_feature(&features, ARM_FEATURE_NEON);
}
- if (extract32(ahcf->isar.mvfr1, 28, 4) == 1) {
- /* FMAC support implies VFPv4 */
- set_feature(&features, ARM_FEATURE_VFP4);
- }
ahcf->features = features;
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
index 0ad96c3500..93ba1448da 100644
--- a/target/arm/kvm64.c
+++ b/target/arm/kvm64.c
@@ -649,7 +649,6 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
* feature bits.
*/
set_feature(&features, ARM_FEATURE_V8);
- set_feature(&features, ARM_FEATURE_VFP4);
set_feature(&features, ARM_FEATURE_NEON);
set_feature(&features, ARM_FEATURE_AARCH64);
set_feature(&features, ARM_FEATURE_PMU);
--
2.20.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH v2 15/17] target/arm: Add formats for some vfp 2 and 3-register insns
2020-02-24 22:22 [PATCH v2 00/17] target/arm: vfp feature and decodetree cleanup Richard Henderson
` (13 preceding siblings ...)
2020-02-24 22:22 ` [PATCH v2 14/17] target/arm: Remove ARM_FEATURE_VFP* Richard Henderson
@ 2020-02-24 22:22 ` Richard Henderson
2020-02-24 22:22 ` [PATCH v2 16/17] target/arm: Split VFM decode Richard Henderson
` (2 subsequent siblings)
17 siblings, 0 replies; 29+ messages in thread
From: Richard Henderson @ 2020-02-24 22:22 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, qemu-arm
Those vfp instructions without extra opcode fields can
share a common @format for brevity.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/vfp.decode | 134 ++++++++++++++++--------------------------
1 file changed, 52 insertions(+), 82 deletions(-)
diff --git a/target/arm/vfp.decode b/target/arm/vfp.decode
index 592fe9e1e4..4f294f88be 100644
--- a/target/arm/vfp.decode
+++ b/target/arm/vfp.decode
@@ -46,6 +46,14 @@
%vmov_imm 16:4 0:4
+@vfp_dnm_s ................................ vm=%vm_sp vn=%vn_sp vd=%vd_sp
+@vfp_dnm_d ................................ vm=%vm_dp vn=%vn_dp vd=%vd_dp
+
+@vfp_dm_ss ................................ vm=%vm_sp vd=%vd_sp
+@vfp_dm_dd ................................ vm=%vm_dp vd=%vd_dp
+@vfp_dm_ds ................................ vm=%vm_sp vd=%vd_dp
+@vfp_dm_sd ................................ vm=%vm_dp vd=%vd_sp
+
# VMOV scalar to general-purpose register; note that this does
# include some Neon cases.
VMOV_to_gp ---- 1110 u:1 1. 1 .... rt:4 1011 ... 1 0000 \
@@ -66,20 +74,15 @@ VDUP ---- 1110 1 b:1 q:1 0 .... rt:4 1011 . 0 e:1 1 0000 \
vn=%vn_dp
VMSR_VMRS ---- 1110 111 l:1 reg:4 rt:4 1010 0001 0000
-VMOV_single ---- 1110 000 l:1 .... rt:4 1010 . 001 0000 \
- vn=%vn_sp
+VMOV_single ---- 1110 000 l:1 .... rt:4 1010 . 001 0000 vn=%vn_sp
-VMOV_64_sp ---- 1100 010 op:1 rt2:4 rt:4 1010 00.1 .... \
- vm=%vm_sp
-VMOV_64_dp ---- 1100 010 op:1 rt2:4 rt:4 1011 00.1 .... \
- vm=%vm_dp
+VMOV_64_sp ---- 1100 010 op:1 rt2:4 rt:4 1010 00.1 .... vm=%vm_sp
+VMOV_64_dp ---- 1100 010 op:1 rt2:4 rt:4 1011 00.1 .... vm=%vm_dp
# Note that the half-precision variants of VLDR and VSTR are
# not part of this decodetree at all because they have bits [9:8] == 0b01
-VLDR_VSTR_sp ---- 1101 u:1 .0 l:1 rn:4 .... 1010 imm:8 \
- vd=%vd_sp
-VLDR_VSTR_dp ---- 1101 u:1 .0 l:1 rn:4 .... 1011 imm:8 \
- vd=%vd_dp
+VLDR_VSTR_sp ---- 1101 u:1 .0 l:1 rn:4 .... 1010 imm:8 vd=%vd_sp
+VLDR_VSTR_dp ---- 1101 u:1 .0 l:1 rn:4 .... 1011 imm:8 vd=%vd_dp
# We split the load/store multiple up into two patterns to avoid
# overlap with other insns in the "Advanced SIMD load/store and 64-bit move"
@@ -100,50 +103,32 @@ VLDM_VSTM_dp ---- 1101 0.1 l:1 rn:4 .... 1011 imm:8 \
vd=%vd_dp p=1 u=0 w=1
# 3-register VFP data-processing; bits [23,21:20,6] identify the operation.
-VMLA_sp ---- 1110 0.00 .... .... 1010 .0.0 .... \
- vm=%vm_sp vn=%vn_sp vd=%vd_sp
-VMLA_dp ---- 1110 0.00 .... .... 1011 .0.0 .... \
- vm=%vm_dp vn=%vn_dp vd=%vd_dp
+VMLA_sp ---- 1110 0.00 .... .... 1010 .0.0 .... @vfp_dnm_s
+VMLA_dp ---- 1110 0.00 .... .... 1011 .0.0 .... @vfp_dnm_d
-VMLS_sp ---- 1110 0.00 .... .... 1010 .1.0 .... \
- vm=%vm_sp vn=%vn_sp vd=%vd_sp
-VMLS_dp ---- 1110 0.00 .... .... 1011 .1.0 .... \
- vm=%vm_dp vn=%vn_dp vd=%vd_dp
+VMLS_sp ---- 1110 0.00 .... .... 1010 .1.0 .... @vfp_dnm_s
+VMLS_dp ---- 1110 0.00 .... .... 1011 .1.0 .... @vfp_dnm_d
-VNMLS_sp ---- 1110 0.01 .... .... 1010 .0.0 .... \
- vm=%vm_sp vn=%vn_sp vd=%vd_sp
-VNMLS_dp ---- 1110 0.01 .... .... 1011 .0.0 .... \
- vm=%vm_dp vn=%vn_dp vd=%vd_dp
+VNMLS_sp ---- 1110 0.01 .... .... 1010 .0.0 .... @vfp_dnm_s
+VNMLS_dp ---- 1110 0.01 .... .... 1011 .0.0 .... @vfp_dnm_d
-VNMLA_sp ---- 1110 0.01 .... .... 1010 .1.0 .... \
- vm=%vm_sp vn=%vn_sp vd=%vd_sp
-VNMLA_dp ---- 1110 0.01 .... .... 1011 .1.0 .... \
- vm=%vm_dp vn=%vn_dp vd=%vd_dp
+VNMLA_sp ---- 1110 0.01 .... .... 1010 .1.0 .... @vfp_dnm_s
+VNMLA_dp ---- 1110 0.01 .... .... 1011 .1.0 .... @vfp_dnm_d
-VMUL_sp ---- 1110 0.10 .... .... 1010 .0.0 .... \
- vm=%vm_sp vn=%vn_sp vd=%vd_sp
-VMUL_dp ---- 1110 0.10 .... .... 1011 .0.0 .... \
- vm=%vm_dp vn=%vn_dp vd=%vd_dp
+VMUL_sp ---- 1110 0.10 .... .... 1010 .0.0 .... @vfp_dnm_s
+VMUL_dp ---- 1110 0.10 .... .... 1011 .0.0 .... @vfp_dnm_d
-VNMUL_sp ---- 1110 0.10 .... .... 1010 .1.0 .... \
- vm=%vm_sp vn=%vn_sp vd=%vd_sp
-VNMUL_dp ---- 1110 0.10 .... .... 1011 .1.0 .... \
- vm=%vm_dp vn=%vn_dp vd=%vd_dp
+VNMUL_sp ---- 1110 0.10 .... .... 1010 .1.0 .... @vfp_dnm_s
+VNMUL_dp ---- 1110 0.10 .... .... 1011 .1.0 .... @vfp_dnm_d
-VADD_sp ---- 1110 0.11 .... .... 1010 .0.0 .... \
- vm=%vm_sp vn=%vn_sp vd=%vd_sp
-VADD_dp ---- 1110 0.11 .... .... 1011 .0.0 .... \
- vm=%vm_dp vn=%vn_dp vd=%vd_dp
+VADD_sp ---- 1110 0.11 .... .... 1010 .0.0 .... @vfp_dnm_s
+VADD_dp ---- 1110 0.11 .... .... 1011 .0.0 .... @vfp_dnm_d
-VSUB_sp ---- 1110 0.11 .... .... 1010 .1.0 .... \
- vm=%vm_sp vn=%vn_sp vd=%vd_sp
-VSUB_dp ---- 1110 0.11 .... .... 1011 .1.0 .... \
- vm=%vm_dp vn=%vn_dp vd=%vd_dp
+VSUB_sp ---- 1110 0.11 .... .... 1010 .1.0 .... @vfp_dnm_s
+VSUB_dp ---- 1110 0.11 .... .... 1011 .1.0 .... @vfp_dnm_d
-VDIV_sp ---- 1110 1.00 .... .... 1010 .0.0 .... \
- vm=%vm_sp vn=%vn_sp vd=%vd_sp
-VDIV_dp ---- 1110 1.00 .... .... 1011 .0.0 .... \
- vm=%vm_dp vn=%vn_dp vd=%vd_dp
+VDIV_sp ---- 1110 1.00 .... .... 1010 .0.0 .... @vfp_dnm_s
+VDIV_dp ---- 1110 1.00 .... .... 1011 .0.0 .... @vfp_dnm_d
VFM_sp ---- 1110 1.01 .... .... 1010 . o2:1 . 0 .... \
vm=%vm_sp vn=%vn_sp vd=%vd_sp o1=1
@@ -159,25 +144,17 @@ VMOV_imm_sp ---- 1110 1.11 .... .... 1010 0000 .... \
VMOV_imm_dp ---- 1110 1.11 .... .... 1011 0000 .... \
vd=%vd_dp imm=%vmov_imm
-VMOV_reg_sp ---- 1110 1.11 0000 .... 1010 01.0 .... \
- vd=%vd_sp vm=%vm_sp
-VMOV_reg_dp ---- 1110 1.11 0000 .... 1011 01.0 .... \
- vd=%vd_dp vm=%vm_dp
+VMOV_reg_sp ---- 1110 1.11 0000 .... 1010 01.0 .... @vfp_dm_ss
+VMOV_reg_dp ---- 1110 1.11 0000 .... 1011 01.0 .... @vfp_dm_dd
-VABS_sp ---- 1110 1.11 0000 .... 1010 11.0 .... \
- vd=%vd_sp vm=%vm_sp
-VABS_dp ---- 1110 1.11 0000 .... 1011 11.0 .... \
- vd=%vd_dp vm=%vm_dp
+VABS_sp ---- 1110 1.11 0000 .... 1010 11.0 .... @vfp_dm_ss
+VABS_dp ---- 1110 1.11 0000 .... 1011 11.0 .... @vfp_dm_dd
-VNEG_sp ---- 1110 1.11 0001 .... 1010 01.0 .... \
- vd=%vd_sp vm=%vm_sp
-VNEG_dp ---- 1110 1.11 0001 .... 1011 01.0 .... \
- vd=%vd_dp vm=%vm_dp
+VNEG_sp ---- 1110 1.11 0001 .... 1010 01.0 .... @vfp_dm_ss
+VNEG_dp ---- 1110 1.11 0001 .... 1011 01.0 .... @vfp_dm_dd
-VSQRT_sp ---- 1110 1.11 0001 .... 1010 11.0 .... \
- vd=%vd_sp vm=%vm_sp
-VSQRT_dp ---- 1110 1.11 0001 .... 1011 11.0 .... \
- vd=%vd_dp vm=%vm_dp
+VSQRT_sp ---- 1110 1.11 0001 .... 1010 11.0 .... @vfp_dm_ss
+VSQRT_dp ---- 1110 1.11 0001 .... 1011 11.0 .... @vfp_dm_dd
VCMP_sp ---- 1110 1.11 010 z:1 .... 1010 e:1 1.0 .... \
vd=%vd_sp vm=%vm_sp
@@ -190,32 +167,26 @@ VCVT_f32_f16 ---- 1110 1.11 0010 .... 1010 t:1 1.0 .... \
VCVT_f64_f16 ---- 1110 1.11 0010 .... 1011 t:1 1.0 .... \
vd=%vd_dp vm=%vm_sp
-# VCVTB and VCVTT to f16: Vd format is always vd_sp; Vm format depends on size bit
+# VCVTB and VCVTT to f16: Vd format is always vd_sp;
+# Vm format depends on size bit
VCVT_f16_f32 ---- 1110 1.11 0011 .... 1010 t:1 1.0 .... \
vd=%vd_sp vm=%vm_sp
VCVT_f16_f64 ---- 1110 1.11 0011 .... 1011 t:1 1.0 .... \
vd=%vd_sp vm=%vm_dp
-VRINTR_sp ---- 1110 1.11 0110 .... 1010 01.0 .... \
- vd=%vd_sp vm=%vm_sp
-VRINTR_dp ---- 1110 1.11 0110 .... 1011 01.0 .... \
- vd=%vd_dp vm=%vm_dp
+VRINTR_sp ---- 1110 1.11 0110 .... 1010 01.0 .... @vfp_dm_ss
+VRINTR_dp ---- 1110 1.11 0110 .... 1011 01.0 .... @vfp_dm_dd
-VRINTZ_sp ---- 1110 1.11 0110 .... 1010 11.0 .... \
- vd=%vd_sp vm=%vm_sp
-VRINTZ_dp ---- 1110 1.11 0110 .... 1011 11.0 .... \
- vd=%vd_dp vm=%vm_dp
+VRINTZ_sp ---- 1110 1.11 0110 .... 1010 11.0 .... @vfp_dm_ss
+VRINTZ_dp ---- 1110 1.11 0110 .... 1011 11.0 .... @vfp_dm_dd
-VRINTX_sp ---- 1110 1.11 0111 .... 1010 01.0 .... \
- vd=%vd_sp vm=%vm_sp
-VRINTX_dp ---- 1110 1.11 0111 .... 1011 01.0 .... \
- vd=%vd_dp vm=%vm_dp
+VRINTX_sp ---- 1110 1.11 0111 .... 1010 01.0 .... @vfp_dm_ss
+VRINTX_dp ---- 1110 1.11 0111 .... 1011 01.0 .... @vfp_dm_dd
-# VCVT between single and double: Vm precision depends on size; Vd is its reverse
-VCVT_sp ---- 1110 1.11 0111 .... 1010 11.0 .... \
- vd=%vd_dp vm=%vm_sp
-VCVT_dp ---- 1110 1.11 0111 .... 1011 11.0 .... \
- vd=%vd_sp vm=%vm_dp
+# VCVT between single and double:
+# Vm precision depends on size; Vd is its reverse
+VCVT_sp ---- 1110 1.11 0111 .... 1010 11.0 .... @vfp_dm_ds
+VCVT_dp ---- 1110 1.11 0111 .... 1011 11.0 .... @vfp_dm_sd
# VCVT from integer to floating point: Vm always single; Vd depends on size
VCVT_int_sp ---- 1110 1.11 1000 .... 1010 s:1 1.0 .... \
@@ -224,8 +195,7 @@ VCVT_int_dp ---- 1110 1.11 1000 .... 1011 s:1 1.0 .... \
vd=%vd_dp vm=%vm_sp
# VJCVT is always dp to sp
-VJCVT ---- 1110 1.11 1001 .... 1011 11.0 .... \
- vd=%vd_sp vm=%vm_dp
+VJCVT ---- 1110 1.11 1001 .... 1011 11.0 .... @vfp_dm_sd
# VCVT between floating-point and fixed-point. The immediate value
# is in the same format as a Vm single-precision register number.
--
2.20.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH v2 16/17] target/arm: Split VFM decode
2020-02-24 22:22 [PATCH v2 00/17] target/arm: vfp feature and decodetree cleanup Richard Henderson
` (14 preceding siblings ...)
2020-02-24 22:22 ` [PATCH v2 15/17] target/arm: Add formats for some vfp 2 and 3-register insns Richard Henderson
@ 2020-02-24 22:22 ` Richard Henderson
2020-02-24 22:22 ` [PATCH v2 17/17] target/arm: Split VMINMAXNM decode Richard Henderson
2020-02-25 17:40 ` [PATCH v2 00/17] target/arm: vfp feature and decodetree cleanup Peter Maydell
17 siblings, 0 replies; 29+ messages in thread
From: Richard Henderson @ 2020-02-24 22:22 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, qemu-arm
Passing the raw o1 and o2 fields from the manual is less
instructive than it might be. Do the full decode and let
the trans_* functions pass in booleans to a helper.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/vfp.decode | 17 +++++------
target/arm/translate-vfp.inc.c | 52 ++++++++++++++++++++++++++++++----
2 files changed, 55 insertions(+), 14 deletions(-)
diff --git a/target/arm/vfp.decode b/target/arm/vfp.decode
index 4f294f88be..5fd70f975a 100644
--- a/target/arm/vfp.decode
+++ b/target/arm/vfp.decode
@@ -130,14 +130,15 @@ VSUB_dp ---- 1110 0.11 .... .... 1011 .1.0 .... @vfp_dnm_d
VDIV_sp ---- 1110 1.00 .... .... 1010 .0.0 .... @vfp_dnm_s
VDIV_dp ---- 1110 1.00 .... .... 1011 .0.0 .... @vfp_dnm_d
-VFM_sp ---- 1110 1.01 .... .... 1010 . o2:1 . 0 .... \
- vm=%vm_sp vn=%vn_sp vd=%vd_sp o1=1
-VFM_dp ---- 1110 1.01 .... .... 1011 . o2:1 . 0 .... \
- vm=%vm_dp vn=%vn_dp vd=%vd_dp o1=1
-VFM_sp ---- 1110 1.10 .... .... 1010 . o2:1 . 0 .... \
- vm=%vm_sp vn=%vn_sp vd=%vd_sp o1=2
-VFM_dp ---- 1110 1.10 .... .... 1011 . o2:1 . 0 .... \
- vm=%vm_dp vn=%vn_dp vd=%vd_dp o1=2
+VFMA_sp ---- 1110 1.10 .... .... 1010 .0. 0 .... @vfp_dnm_s
+VFMS_sp ---- 1110 1.10 .... .... 1010 .1. 0 .... @vfp_dnm_s
+VFNMA_sp ---- 1110 1.01 .... .... 1010 .0. 0 .... @vfp_dnm_s
+VFNMS_sp ---- 1110 1.01 .... .... 1010 .1. 0 .... @vfp_dnm_s
+
+VFMA_dp ---- 1110 1.10 .... .... 1011 .0.0 .... @vfp_dnm_d
+VFMS_dp ---- 1110 1.10 .... .... 1011 .1.0 .... @vfp_dnm_d
+VFNMA_dp ---- 1110 1.01 .... .... 1011 .0.0 .... @vfp_dnm_d
+VFNMS_dp ---- 1110 1.01 .... .... 1011 .1.0 .... @vfp_dnm_d
VMOV_imm_sp ---- 1110 1.11 .... .... 1010 0000 .... \
vd=%vd_sp imm=%vmov_imm
diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c
index 1964af3ea5..41aa67c133 100644
--- a/target/arm/translate-vfp.inc.c
+++ b/target/arm/translate-vfp.inc.c
@@ -1784,7 +1784,7 @@ static bool trans_VDIV_dp(DisasContext *s, arg_VDIV_dp *a)
return do_vfp_3op_dp(s, gen_helper_vfp_divd, a->vd, a->vn, a->vm, false);
}
-static bool trans_VFM_sp(DisasContext *s, arg_VFM_sp *a)
+static bool do_vfm_sp(DisasContext *s, arg_VFMA_sp *a, bool neg_n, bool neg_d)
{
/*
* VFNMA : fd = muladd(-fd, fn, fm)
@@ -1828,12 +1828,12 @@ static bool trans_VFM_sp(DisasContext *s, arg_VFM_sp *a)
neon_load_reg32(vn, a->vn);
neon_load_reg32(vm, a->vm);
- if (a->o2) {
+ if (neg_n) {
/* VFNMS, VFMS */
gen_helper_vfp_negs(vn, vn);
}
neon_load_reg32(vd, a->vd);
- if (a->o1 & 1) {
+ if (neg_d) {
/* VFNMA, VFNMS */
gen_helper_vfp_negs(vd, vd);
}
@@ -1849,7 +1849,27 @@ static bool trans_VFM_sp(DisasContext *s, arg_VFM_sp *a)
return true;
}
-static bool trans_VFM_dp(DisasContext *s, arg_VFM_dp *a)
+static bool trans_VFMA_sp(DisasContext *s, arg_VFMA_sp *a)
+{
+ return do_vfm_sp(s, a, false, false);
+}
+
+static bool trans_VFMS_sp(DisasContext *s, arg_VFMS_sp *a)
+{
+ return do_vfm_sp(s, a, true, false);
+}
+
+static bool trans_VFNMA_sp(DisasContext *s, arg_VFNMA_sp *a)
+{
+ return do_vfm_sp(s, a, false, true);
+}
+
+static bool trans_VFNMS_sp(DisasContext *s, arg_VFNMS_sp *a)
+{
+ return do_vfm_sp(s, a, true, true);
+}
+
+static bool do_vfm_dp(DisasContext *s, arg_VFMA_dp *a, bool neg_n, bool neg_d)
{
/*
* VFNMA : fd = muladd(-fd, fn, fm)
@@ -1905,12 +1925,12 @@ static bool trans_VFM_dp(DisasContext *s, arg_VFM_dp *a)
neon_load_reg64(vn, a->vn);
neon_load_reg64(vm, a->vm);
- if (a->o2) {
+ if (neg_n) {
/* VFNMS, VFMS */
gen_helper_vfp_negd(vn, vn);
}
neon_load_reg64(vd, a->vd);
- if (a->o1 & 1) {
+ if (neg_d) {
/* VFNMA, VFNMS */
gen_helper_vfp_negd(vd, vd);
}
@@ -1926,6 +1946,26 @@ static bool trans_VFM_dp(DisasContext *s, arg_VFM_dp *a)
return true;
}
+static bool trans_VFMA_dp(DisasContext *s, arg_VFMA_dp *a)
+{
+ return do_vfm_dp(s, a, false, false);
+}
+
+static bool trans_VFMS_dp(DisasContext *s, arg_VFMS_dp *a)
+{
+ return do_vfm_dp(s, a, true, false);
+}
+
+static bool trans_VFNMA_dp(DisasContext *s, arg_VFNMA_dp *a)
+{
+ return do_vfm_dp(s, a, false, true);
+}
+
+static bool trans_VFNMS_dp(DisasContext *s, arg_VFNMS_dp *a)
+{
+ return do_vfm_dp(s, a, true, true);
+}
+
static bool trans_VMOV_imm_sp(DisasContext *s, arg_VMOV_imm_sp *a)
{
uint32_t delta_d = 0;
--
2.20.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH v2 17/17] target/arm: Split VMINMAXNM decode
2020-02-24 22:22 [PATCH v2 00/17] target/arm: vfp feature and decodetree cleanup Richard Henderson
` (15 preceding siblings ...)
2020-02-24 22:22 ` [PATCH v2 16/17] target/arm: Split VFM decode Richard Henderson
@ 2020-02-24 22:22 ` Richard Henderson
2020-02-25 17:40 ` [PATCH v2 00/17] target/arm: vfp feature and decodetree cleanup Peter Maydell
17 siblings, 0 replies; 29+ messages in thread
From: Richard Henderson @ 2020-02-24 22:22 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, qemu-arm
Passing the raw op field from the manual is less instructive
than it might be. Do the full decode and use the existing
helpers to perform the expansion.
Since these are v8 insns, VECLEN+VECSTRIDE are already RES0.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/vfp-uncond.decode | 12 ++--
target/arm/translate-vfp.inc.c | 109 +++++++++++----------------------
2 files changed, 44 insertions(+), 77 deletions(-)
diff --git a/target/arm/vfp-uncond.decode b/target/arm/vfp-uncond.decode
index 5af1f2ee66..34ca164266 100644
--- a/target/arm/vfp-uncond.decode
+++ b/target/arm/vfp-uncond.decode
@@ -41,15 +41,19 @@
%vd_dp 22:1 12:4
%vd_sp 12:4 22:1
+@vfp_dnm_s ................................ vm=%vm_sp vn=%vn_sp vd=%vd_sp
+@vfp_dnm_d ................................ vm=%vm_dp vn=%vn_dp vd=%vd_dp
+
VSEL 1111 1110 0. cc:2 .... .... 1010 .0.0 .... \
vm=%vm_sp vn=%vn_sp vd=%vd_sp dp=0
VSEL 1111 1110 0. cc:2 .... .... 1011 .0.0 .... \
vm=%vm_dp vn=%vn_dp vd=%vd_dp dp=1
-VMINMAXNM 1111 1110 1.00 .... .... 1010 . op:1 .0 .... \
- vm=%vm_sp vn=%vn_sp vd=%vd_sp dp=0
-VMINMAXNM 1111 1110 1.00 .... .... 1011 . op:1 .0 .... \
- vm=%vm_dp vn=%vn_dp vd=%vd_dp dp=1
+VMAXNM_sp 1111 1110 1.00 .... .... 1010 .0.0 .... @vfp_dnm_s
+VMINNM_sp 1111 1110 1.00 .... .... 1010 .1.0 .... @vfp_dnm_s
+
+VMAXNM_dp 1111 1110 1.00 .... .... 1011 .0.0 .... @vfp_dnm_d
+VMINNM_dp 1111 1110 1.00 .... .... 1011 .1.0 .... @vfp_dnm_d
VRINT 1111 1110 1.11 10 rm:2 .... 1010 01.0 .... \
vm=%vm_sp vd=%vd_sp dp=0
diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c
index 41aa67c133..b087bbd812 100644
--- a/target/arm/translate-vfp.inc.c
+++ b/target/arm/translate-vfp.inc.c
@@ -322,79 +322,6 @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a)
return true;
}
-static bool trans_VMINMAXNM(DisasContext *s, arg_VMINMAXNM *a)
-{
- uint32_t rd, rn, rm;
- bool dp = a->dp;
- bool vmin = a->op;
- TCGv_ptr fpst;
-
- if (!dc_isar_feature(aa32_vminmaxnm, s)) {
- return false;
- }
-
- if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
- return false;
- }
-
- /* UNDEF accesses to D16-D31 if they don't exist */
- if (dp && !dc_isar_feature(aa32_simd_r32, s) &&
- ((a->vm | a->vn | a->vd) & 0x10)) {
- return false;
- }
-
- rd = a->vd;
- rn = a->vn;
- rm = a->vm;
-
- if (!vfp_access_check(s)) {
- return true;
- }
-
- fpst = get_fpstatus_ptr(0);
-
- if (dp) {
- TCGv_i64 frn, frm, dest;
-
- frn = tcg_temp_new_i64();
- frm = tcg_temp_new_i64();
- dest = tcg_temp_new_i64();
-
- neon_load_reg64(frn, rn);
- neon_load_reg64(frm, rm);
- if (vmin) {
- gen_helper_vfp_minnumd(dest, frn, frm, fpst);
- } else {
- gen_helper_vfp_maxnumd(dest, frn, frm, fpst);
- }
- neon_store_reg64(dest, rd);
- tcg_temp_free_i64(frn);
- tcg_temp_free_i64(frm);
- tcg_temp_free_i64(dest);
- } else {
- TCGv_i32 frn, frm, dest;
-
- frn = tcg_temp_new_i32();
- frm = tcg_temp_new_i32();
- dest = tcg_temp_new_i32();
-
- neon_load_reg32(frn, rn);
- neon_load_reg32(frm, rm);
- if (vmin) {
- gen_helper_vfp_minnums(dest, frn, frm, fpst);
- } else {
- gen_helper_vfp_maxnums(dest, frn, frm, fpst);
- }
- neon_store_reg32(dest, rd);
- tcg_temp_free_i32(frn);
- tcg_temp_free_i32(frm);
- tcg_temp_free_i32(dest);
- }
-
- tcg_temp_free_ptr(fpst);
- return true;
-}
-
/*
* Table for converting the most common AArch32 encoding of
* rounding mode to arm_fprounding order (which matches the
@@ -1784,6 +1711,42 @@ static bool trans_VDIV_dp(DisasContext *s, arg_VDIV_dp *a)
return do_vfp_3op_dp(s, gen_helper_vfp_divd, a->vd, a->vn, a->vm, false);
}
+static bool trans_VMINNM_sp(DisasContext *s, arg_VMINNM_sp *a)
+{
+ if (!dc_isar_feature(aa32_vminmaxnm, s)) {
+ return false;
+ }
+ return do_vfp_3op_sp(s, gen_helper_vfp_minnums,
+ a->vd, a->vn, a->vm, false);
+}
+
+static bool trans_VMAXNM_sp(DisasContext *s, arg_VMAXNM_sp *a)
+{
+ if (!dc_isar_feature(aa32_vminmaxnm, s)) {
+ return false;
+ }
+ return do_vfp_3op_sp(s, gen_helper_vfp_maxnums,
+ a->vd, a->vn, a->vm, false);
+}
+
+static bool trans_VMINNM_dp(DisasContext *s, arg_VMINNM_dp *a)
+{
+ if (!dc_isar_feature(aa32_vminmaxnm, s)) {
+ return false;
+ }
+ return do_vfp_3op_dp(s, gen_helper_vfp_minnumd,
+ a->vd, a->vn, a->vm, false);
+}
+
+static bool trans_VMAXNM_dp(DisasContext *s, arg_VMAXNM_dp *a)
+{
+ if (!dc_isar_feature(aa32_vminmaxnm, s)) {
+ return false;
+ }
+ return do_vfp_3op_dp(s, gen_helper_vfp_maxnumd,
+ a->vd, a->vn, a->vm, false);
+}
+
static bool do_vfm_sp(DisasContext *s, arg_VFMA_sp *a, bool neg_n, bool neg_d)
{
/*
--
2.20.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* Re: [PATCH v2 00/17] target/arm: vfp feature and decodetree cleanup
2020-02-24 22:22 [PATCH v2 00/17] target/arm: vfp feature and decodetree cleanup Richard Henderson
` (16 preceding siblings ...)
2020-02-24 22:22 ` [PATCH v2 17/17] target/arm: Split VMINMAXNM decode Richard Henderson
@ 2020-02-25 17:40 ` Peter Maydell
17 siblings, 0 replies; 29+ messages in thread
From: Peter Maydell @ 2020-02-25 17:40 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-arm, QEMU Developers
On Mon, 24 Feb 2020 at 22:22, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> The main goal of the patchset is to move the ARM_FEATURE_VFP test from
> outside of the disas_vfp_insn() to inside each of the trans_* functions,
> so that we get the proper ISA check for each case. At the end of that,
> it is easy to eliminate all of the remaining tests vs ARM_FEATURE_VFP*
> in favor of the preferred ISAR tests. Finally, there are a couple of
> cleanups to vfp.decode to make things a bit more legible.
>
> Changes for v2:
> * Replace aa32_simd_r16 by aa32_vfp_simd.
> * Add aa64_fp_simd, aa32_vfp.
> * Improve aa64 has_vfp/has_neon check.
> * Fix some "any" tests.
>
I've dropped patch 5 and applied the rest to target-arm.next.
thanks
-- PMM
^ permalink raw reply [flat|nested] 29+ messages in thread