From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39372) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Wntkf-0000rP-TB for qemu-devel@nongnu.org; Fri, 23 May 2014 13:59:36 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WntkY-0004JG-K2 for qemu-devel@nongnu.org; Fri, 23 May 2014 13:59:29 -0400 Received: from mail-la0-f44.google.com ([209.85.215.44]:57846) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WntkY-0004IX-EB for qemu-devel@nongnu.org; Fri, 23 May 2014 13:59:22 -0400 Received: by mail-la0-f44.google.com with SMTP id hr17so4549422lab.31 for ; Fri, 23 May 2014 10:59:21 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: <1399041202-26184-7-git-send-email-pbonzini@redhat.com> References: <1399041202-26184-1-git-send-email-pbonzini@redhat.com> <1399041202-26184-7-git-send-email-pbonzini@redhat.com> From: Peter Maydell Date: Fri, 23 May 2014 18:59:01 +0100 Message-ID: Content-Type: text/plain; charset=UTF-8 Subject: Re: [Qemu-devel] [PATCH v2 6/8] cpu: make CPU_INTERRUPT_RESET available on all targets List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Paolo Bonzini Cc: QEMU Developers On 2 May 2014 15:33, Paolo Bonzini wrote: > On the x86, some devices need access to the CPU reset pin (INIT#). > Provide a generic service to do this, using one of the internal > cpu_interrupt targets. Generalize the PPC-specific code for > CPU_INTERRUPT_RESET to other targets. > > Since PPC does not support migration across QEMU versions (its > machine types are not versioned yet), I picked the value that > is used on x86, CPU_INTERRUPT_TGT_INT_1. Consequently, TGT_INT_2 > and TGT_INT_3 are shifted down by one while keeping their value. > > Reviewed-by: Anthony Liguori > Signed-off-by: Paolo Bonzini > --- > cpu-exec.c | 23 +++++++++++++---------- > cpus.c | 9 +++++++++ > include/exec/cpu-all.h | 8 +++++--- > include/sysemu/cpus.h | 1 + > target-i386/cpu.h | 7 ++++--- > target-ppc/cpu.h | 3 --- > 6 files changed, 32 insertions(+), 19 deletions(-) > > diff --git a/cpu-exec.c b/cpu-exec.c > index 2f54054..38e5f02 100644 > --- a/cpu-exec.c > +++ b/cpu-exec.c > @@ -336,19 +336,25 @@ int cpu_exec(CPUArchState *env) > } > #endif > #if defined(TARGET_I386) > + if (interrupt_request & CPU_INTERRUPT_INIT) { > + cpu_svm_check_intercept_param(env, SVM_EXIT_INIT, 0); > + do_cpu_init(x86_cpu); > + cpu->exception_index = EXCP_HALTED; > + cpu_loop_exit(cpu); > + } > +#else > + if (interrupt_request & CPU_INTERRUPT_RESET) { > + cpu_reset(cpu); > + } > +#endif I was looking at cleaning up the horrible ifdef ladder a little lower in this function, and I noticed this code had been added recently. Why is TARGET_I386 a special case here? New #ifdef TARGET_* here are pretty bogus and we should try to avoid them. Could we have the CPU_INTERRUPT_RESET check be all-targets and move the INTERRUPT_INIT check down below it to be with all the other x86 specific interrupt test code ? thanks -- PMM