* [Qemu-devel] [PATCH 1/2] ARM: Exynos4210: Drop gic_cpu_write() after initialization.
2012-04-04 6:39 [Qemu-devel] [PATCH 0/2] ARM: Exynos4210: Fix GIC initialization and Combiner operation Evgeny Voevodin
@ 2012-04-04 6:39 ` Evgeny Voevodin
2012-04-04 9:38 ` Peter Maydell
2012-04-04 6:39 ` [Qemu-devel] [PATCH 2/2] hw/exynos4210_combiner.c: Drop excessive read/write access check Evgeny Voevodin
1 sibling, 1 reply; 5+ messages in thread
From: Evgeny Voevodin @ 2012-04-04 6:39 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, i.mitsyanko, Evgeny Voevodin, kyungmin.park,
d.solodkiy, m.kozlov
Remove gic_cpu_write() call after initialization that was emulating
functionality of earliest SOC bootloader which enables external
GIC CPU1 interface. Instead introduce Exynos4210-specific secondary
CPU bootloader, which enables both Internal and External GIC CPU1
interfaces.
Signed-off-by: Evgeny Voevodin <e.voevodin@samsung.com>
---
hw/exynos4210.c | 30 ++++++++++++++++++++++++++++++
hw/exynos4210.h | 3 +++
hw/exynos4210_gic.c | 2 --
hw/exynos4_boards.c | 1 +
4 files changed, 34 insertions(+), 2 deletions(-)
diff --git a/hw/exynos4210.c b/hw/exynos4210.c
index f904370..afc4bdc 100644
--- a/hw/exynos4210.c
+++ b/hw/exynos4210.c
@@ -25,6 +25,7 @@
#include "sysemu.h"
#include "sysbus.h"
#include "arm-misc.h"
+#include "loader.h"
#include "exynos4210.h"
#define EXYNOS4210_CHIPID_ADDR 0x10000000
@@ -64,6 +65,35 @@
static uint8_t chipid_and_omr[] = { 0x11, 0x02, 0x21, 0x43,
0x09, 0x00, 0x00, 0x00 };
+void exynos4210_write_secondary(CPUARMState *env,
+ const struct arm_boot_info *info)
+{
+ int n;
+ uint32_t smpboot[] = {
+ 0xe59f3024, /* ldr r3, External gic_cpu_if */
+ 0xe59f2024, /* ldr r2, Internal gic_cpu_if */
+ 0xe59f0024, /* ldr r0, startaddr */
+ 0xe3a01001, /* mov r1, #1 */
+ 0xe5821000, /* str r1, [r2] */
+ 0xe5831000, /* str r1, [r3] */
+ 0xe320f003, /* wfi */
+ 0xe5901000, /* ldr r1, [r0] */
+ 0xe1110001, /* tst r1, r1 */
+ 0x0afffffb, /* beq <wfi> */
+ 0xe12fff11, /* bx r1 */
+ EXYNOS4210_EXT_GIC_CPU_BASE_ADDR,
+ 0, /* gic_cpu_if: base address of Internal GIC CPU interface */
+ 0 /* bootreg: Boot register address is held here */
+ };
+ smpboot[ARRAY_SIZE(smpboot) - 1] = info->smp_bootreg_addr;
+ smpboot[ARRAY_SIZE(smpboot) - 2] = info->gic_cpu_if_addr;
+ for (n = 0; n < ARRAY_SIZE(smpboot); n++) {
+ smpboot[n] = tswap32(smpboot[n]);
+ }
+ rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot),
+ info->smp_loader_start);
+}
+
Exynos4210State *exynos4210_init(MemoryRegion *system_mem,
unsigned long ram_size)
{
diff --git a/hw/exynos4210.h b/hw/exynos4210.h
index c112e03..f7c7027 100644
--- a/hw/exynos4210.h
+++ b/hw/exynos4210.h
@@ -97,6 +97,9 @@ typedef struct Exynos4210State {
MemoryRegion bootreg_mem;
} Exynos4210State;
+void exynos4210_write_secondary(CPUARMState *env,
+ const struct arm_boot_info *info);
+
Exynos4210State *exynos4210_init(MemoryRegion *system_mem,
unsigned long ram_size);
diff --git a/hw/exynos4210_gic.c b/hw/exynos4210_gic.c
index ec13140..3ba9063 100644
--- a/hw/exynos4210_gic.c
+++ b/hw/exynos4210_gic.c
@@ -321,8 +321,6 @@ static int exynos4210_gic_init(SysBusDevice *dev)
sysbus_init_mmio(dev, &s->cpu_container);
sysbus_init_mmio(dev, &s->dist_container);
- gic_cpu_write(&s->gic, 1, 0, 1);
-
return 0;
}
diff --git a/hw/exynos4_boards.c b/hw/exynos4_boards.c
index 553a02b..ea32c51 100644
--- a/hw/exynos4_boards.c
+++ b/hw/exynos4_boards.c
@@ -70,6 +70,7 @@ static struct arm_boot_info exynos4_board_binfo = {
.loader_start = EXYNOS4210_BASE_BOOT_ADDR,
.smp_loader_start = EXYNOS4210_SMP_BOOT_ADDR,
.nb_cpus = EXYNOS4210_NCPUS,
+ .write_secondary_boot = exynos4210_write_secondary,
};
static QEMUMachine exynos4_machines[EXYNOS4_NUM_OF_BOARDS];
--
1.7.5.4
^ permalink raw reply related [flat|nested] 5+ messages in thread* [Qemu-devel] [PATCH 2/2] hw/exynos4210_combiner.c: Drop excessive read/write access check.
2012-04-04 6:39 [Qemu-devel] [PATCH 0/2] ARM: Exynos4210: Fix GIC initialization and Combiner operation Evgeny Voevodin
2012-04-04 6:39 ` [Qemu-devel] [PATCH 1/2] ARM: Exynos4210: Drop gic_cpu_write() after initialization Evgeny Voevodin
@ 2012-04-04 6:39 ` Evgeny Voevodin
2012-04-04 9:39 ` Peter Maydell
1 sibling, 1 reply; 5+ messages in thread
From: Evgeny Voevodin @ 2012-04-04 6:39 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, i.mitsyanko, Evgeny Voevodin, kyungmin.park,
d.solodkiy, m.kozlov
Access to reserved area at offset higher than 0x3c is allowed in
External Combiner. Samsung Galaxy Kernel implements this. So, drop
excessive checks in read/write functions.
Signed-off-by: Evgeny Voevodin <e.voevodin@samsung.com>
---
hw/exynos4210_combiner.c | 10 ----------
1 files changed, 0 insertions(+), 10 deletions(-)
diff --git a/hw/exynos4210_combiner.c b/hw/exynos4210_combiner.c
index 6110c19..80af22c 100644
--- a/hw/exynos4210_combiner.c
+++ b/hw/exynos4210_combiner.c
@@ -184,11 +184,6 @@ exynos4210_combiner_read(void *opaque, target_phys_addr_t offset, unsigned size)
uint32_t reg_n; /* Register number inside the quad */
uint32_t val;
- if (s->external && (offset > 0x3c && offset != 0x100)) {
- hw_error("exynos4210.combiner: unallowed read access at offset 0x"
- TARGET_FMT_plx "\n", offset);
- }
-
req_quad_base_n = offset >> 4;
grp_quad_base_n = req_quad_base_n << 2;
reg_n = (offset - (req_quad_base_n << 4)) >> 2;
@@ -281,11 +276,6 @@ static void exynos4210_combiner_write(void *opaque, target_phys_addr_t offset,
uint32_t grp_quad_base_n; /* Base of group quad */
uint32_t reg_n; /* Register number inside the quad */
- if (s->external && (offset > 0x3c && offset != 0x100)) {
- hw_error("exynos4210.combiner: unallowed write access at offset 0x"
- TARGET_FMT_plx "\n", offset);
- }
-
req_quad_base_n = offset >> 4;
grp_quad_base_n = req_quad_base_n << 2;
reg_n = (offset - (req_quad_base_n << 4)) >> 2;
--
1.7.5.4
^ permalink raw reply related [flat|nested] 5+ messages in thread