From: Peter Maydell <peter.maydell@linaro.org>
To: Alessandro Di Federico <ale+qemu@clearmind.me>
Cc: QEMU Developers <qemu-devel@nongnu.org>
Subject: Re: [Qemu-devel] [RFC PATCH 0/3] Preparing the build system for libtcg
Date: Tue, 7 Feb 2017 11:40:38 +0000 [thread overview]
Message-ID: <CAFEAcA_RLBgpOg2eBGujSGOduAOp8VpaaE6EfM6D+j05AMxquw@mail.gmail.com> (raw)
In-Reply-To: <20170121084600.5860-1-ale+qemu@clearmind.me>
On 21 January 2017 at 08:45, Alessandro Di Federico
<ale+qemu@clearmind.me> wrote:
> This series of patches introduce a set of changes, mainly to the QEMU
> build system, to open the way to implementing "libtcg", i.e., using
> QEMU's tiny code generator frontends as a library.
>
> For the initial proposal, please see the related discussion:
>
> http://lists.nongnu.org/archive/html/qemu-devel/2016-11/msg04847.html
>
> The idea is to build a PIC version of QEMU embedding only what's
> required to use the TCG frontend (typically
> target/$arch/translate.c). To achieve this, some functions have been
> moved out of translate.c to reduce the coupling with the other object
> files.
>
> All the configurations available on Linux and FreeBSD still build fine
> (without warnings).
>
> The last commit also introduces the libtcg/ directory and a series of
> *-libtcg targets (similar to the *-{bsd,linux}-user) with the bare
> minimum skeleton for the actual implementation and some dummy references
> to some functions that in my previous implementation of libtcg were
> required, to make sure that all the required object files are linked in.
So I guess my question here is: how are we defining the boundary
between libtcg and everything else? How do we disentangle or
abstract away cleanly the parts of a guest CPU frontend that are
annoyingly tightly coupled to the rest of the system model? Some
examples:
* CPU instructions for reading timers (either cycle counts,
or real-time timers)
* CPU instructions that need to update interrupt controller
state (the ARM M profile CPUs have a bunch of these, as
do GICv3 ARM CPUs)
* CPUs where some CPU state is accessed via memory mapped
registers (again, M profile CPUs have a lot of that)
I think this is overall a good idea but I think I'll find it
easier to review if I have a more solid idea of the design
principles and where we're trying to draw dividing lines
in the tricky cases.
thanks
-- PMM
prev parent reply other threads:[~2017-02-07 11:41 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-01-21 8:45 [Qemu-devel] [RFC PATCH 0/3] Preparing the build system for libtcg Alessandro Di Federico
2017-01-21 8:45 ` [Qemu-devel] [RFC PATCH 1/3] Factor out {linux,bsd}-user/qemu.h Alessandro Di Federico
2017-01-24 10:10 ` [Qemu-devel] [RFC PATCH 1/3] Factor out {linux, bsd}-user/qemu.h Marc-André Lureau
2017-01-25 7:37 ` Alessandro Di Federico
2017-01-24 11:18 ` Peter Maydell
2017-01-25 7:38 ` Alessandro Di Federico
2017-02-07 17:25 ` Peter Maydell
2017-01-21 8:45 ` [Qemu-devel] [RFC PATCH 2/3] *-user targets object files decoupling Alessandro Di Federico
2017-01-24 10:09 ` Marc-André Lureau
2017-01-25 7:38 ` Alessandro Di Federico
2017-01-21 8:46 ` [Qemu-devel] [RFC PATCH 3/3] Introduce libtcg infrastructure Alessandro Di Federico
2017-01-24 10:08 ` Marc-André Lureau
2017-01-25 7:37 ` Alessandro Di Federico
2017-01-21 9:01 ` [Qemu-devel] [RFC PATCH 0/3] Preparing the build system for libtcg no-reply
2017-02-07 11:40 ` Peter Maydell [this message]
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