Re: [Qemu-devel] [PATCH v2 1/3] target/arm: Remove writefn from TTBR0_EL3

[Peter Maydell <peter.maydell@linaro.org>]

On 19 October 2018 at 02:56, Richard Henderson
<richard.henderson@linaro.org> wrote:
> The EL3 version of this register does not include an ASID,
> and so the tlb_flush performed by vmsa_ttbr_write is not needed.
>
> Reviewed-by: Aaron Lindsay <aaron@os.amperecomputing.com>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>  target/arm/helper.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index e3946562aa..24bbde4f76 100644
> --- a/target/arm/helper.c
> +++ b/target/arm/helper.c
> @@ -4214,7 +4214,7 @@ static const ARMCPRegInfo el3_cp_reginfo[] = {
>        .fieldoffset = offsetof(CPUARMState, cp15.mvbar) },
>      { .name = "TTBR0_EL3", .state = ARM_CP_STATE_AA64,
>        .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 0,
> -      .access = PL3_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0,
> +      .access = PL3_RW, .resetvalue = 0,
>        .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[3]) },
>      { .name = "TCR_EL3", .state = ARM_CP_STATE_AA64,
>        .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 2,
> --
> 2.17.2
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

thanks
-- PMM