From: Peter Maydell <peter.maydell@linaro.org>
To: "Alex Bennée" <alex.bennee@linaro.org>
Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, qemu-stable@nongnu.org
Subject: Re: [PATCH v3 3/9] target/arm: Make CNTPS_* UNDEF from Secure EL1 when Secure EL2 is enabled
Date: Fri, 21 Feb 2025 18:25:19 +0000 [thread overview]
Message-ID: <CAFEAcA_UsSNGWUE8uzScepxQoPydd-=s2UpUeRxiN_WSdd11XA@mail.gmail.com> (raw)
In-Reply-To: <87wmdjgor4.fsf@draig.linaro.org>
On Fri, 21 Feb 2025 at 18:02, Alex Bennée <alex.bennee@linaro.org> wrote:
>
> Peter Maydell <peter.maydell@linaro.org> writes:
>
> > When we added Secure EL2 support, we missed that this needs an update
> > to the access code for the EL3 physical timer registers. These are
> > supposed to UNDEF from Secure EL1 when Secure EL2 is enabled.
> >
> > Cc: qemu-stable@nongnu.org
> > Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> > ---
> > target/arm/helper.c | 3 +++
> > 1 file changed, 3 insertions(+)
> >
> > diff --git a/target/arm/helper.c b/target/arm/helper.c
> > index ac8cb428925..7ec1e6cfaab 100644
> > --- a/target/arm/helper.c
> > +++ b/target/arm/helper.c
> > @@ -2387,6 +2387,9 @@ static CPAccessResult gt_stimer_access(CPUARMState *env,
> > if (!arm_is_secure(env)) {
> > return CP_ACCESS_UNDEFINED;
> > }
>
> Hmm this failed to apply as b4d3978c2f (target-arm: Add the AArch64 view
> of the Secure physical timer) has the above as CP_ACCESS_TRAP. I guess
> because I didn't apply 20250130182309.717346-1-peter.maydell@linaro.org.
> I guess this needs fixing up for stable.
There is a Based-on: tag in the cover letter which will tell you
what this series should be based on if you want to apply it.
Yes, we'll need to either tweak this commit for stable
(i.e. use CP_ACCESS_TRAP_UNCATEGORIZED instead of UNDEFINED)
or else pull in the refactoring patches it depends on.
thanks
-- PMM
next prev parent reply other threads:[~2025-02-21 18:26 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-04 12:50 [PATCH v3 0/9] target/arm: Implement SEL2 physical and virtual timers Peter Maydell
2025-02-04 12:50 ` [PATCH v3 1/9] target/arm: Apply correct timer offset when calculating deadlines Peter Maydell
2025-02-26 9:04 ` Alex Bennée
2025-02-04 12:50 ` [PATCH v3 2/9] target/arm: Don't apply CNTVOFF_EL2 for EL2_VIRT timer Peter Maydell
2025-02-26 9:05 ` Alex Bennée
2025-02-04 12:50 ` [PATCH v3 3/9] target/arm: Make CNTPS_* UNDEF from Secure EL1 when Secure EL2 is enabled Peter Maydell
2025-02-21 18:02 ` Alex Bennée
2025-02-21 18:25 ` Peter Maydell [this message]
2025-02-04 12:50 ` [PATCH v3 4/9] target/arm: Always apply CNTVOFF_EL2 for CNTV_TVAL_EL02 accesses Peter Maydell
2025-02-26 9:06 ` Alex Bennée
2025-02-04 12:50 ` [PATCH v3 5/9] target/arm: Refactor handling of timer offset for direct register accesses Peter Maydell
2025-02-26 9:07 ` Alex Bennée
2025-02-04 12:50 ` [PATCH v3 6/9] target/arm: Implement SEL2 physical and virtual timers Peter Maydell
2025-02-04 12:50 ` [PATCH v3 7/9] target/arm: document the architectural names of our GTIMERs Peter Maydell
2025-02-04 12:50 ` [PATCH v3 8/9] hw/arm: enable secure EL2 timers for virt machine Peter Maydell
2025-02-04 12:50 ` [PATCH v3 9/9] hw/arm: enable secure EL2 timers for sbsa machine Peter Maydell
2025-02-21 11:06 ` [PATCH v3 0/9] target/arm: Implement SEL2 physical and virtual timers Peter Maydell
2025-03-09 5:24 ` Michael Tokarev
2025-03-09 12:05 ` Alex Bennée
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