From: Peter Maydell <peter.maydell@linaro.org>
To: Alistair Francis <alistair23@gmail.com>
Cc: qemu-devel@nongnu.org, Alistair Francis <alistair.francis@wdc.com>
Subject: Re: [PULL 00/47] riscv-to-apply queue
Date: Fri, 13 Sep 2024 11:37:18 +0100 [thread overview]
Message-ID: <CAFEAcA_W5bTcCmeAx+dB4+djcUHzjRH4GfBobaHot5VjE+x05g@mail.gmail.com> (raw)
In-Reply-To: <20240912052953.2552501-1-alistair.francis@wdc.com>
On Thu, 12 Sept 2024 at 06:30, Alistair Francis <alistair23@gmail.com> wrote:
>
> The following changes since commit a4eb31c678400472de0b4915b9154a7c20d8332f:
>
> Merge tag 'pull-testing-gdbstub-oct-100924-1' of https://gitlab.com/stsquad/qemu into staging (2024-09-11 13:17:29 +0100)
>
> are available in the Git repository at:
>
> https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20240912-1
>
> for you to fetch changes up to 90d5d3c1115399d8e27621efd69dfa74a35a4932:
>
> hw/intc: riscv-imsic: Fix interrupt state updates. (2024-09-12 15:05:10 +1000)
>
> ----------------------------------------------------------------
> RISC-V PR for 9.2
>
> * Add a property to set vl to ceil(AVL/2)
> * Enable numamem testing for RISC-V
> * Consider MISA bit choice in implied rule
> * Fix the za64rs priv spec requirements
> * Enable Bit Manip for OpenTitan Ibex CPU
> * Fix the group bit setting of AIA with KVM
> * Stop timer with infinite timecmp
> * Add 'fcsr' register to QEMU log as a part of F extension
> * Fix riscv64 build on musl libc
> * Add preliminary textra trigger CSR functions
> * RISC-V IOMMU support
> * RISC-V bsd-user support
> * Respect firmware ELF entry point
> * Add Svvptc extension support
> * Fix masking of rv32 physical address
> * Fix linking problem with semihosting disabled
> * Fix IMSIC interrupt state updates
Hi; this fails to build on FreeBSD:
https://gitlab.com/qemu-project/qemu/-/jobs/7817823771
In file included from ../bsd-user/elfload.c:31:
In file included from ../bsd-user/freebsd/target_os_stack.h:24:
../bsd-user/riscv/target_arch_sigtramp.h:32:33: error: initializer
element is not a compile-time constant
32 | /*2*/ const_le32(0x00050513 + (sigf_uc << 20)), /*addi a0,a0,sigf_uc*/
| ~~~~~~~~~~~^~~~~~~~~~~~~~~~~
/tmp/cirrus-ci-build/include/qemu/bswap.h:168:26: note: expanded from
macro 'const_le32'
168 | # define const_le32(_x) (_x)
| ^~
and
In file included from ../bsd-user/main.c:53:
../bsd-user/riscv/target_arch_cpu.h:126:13: error: call to undeclared
function 'force_sig_fault'; ISO C99 and later do not support implicit
function declarations [-Werror,-Wimplicit-function-declaration]
126 | force_sig_fault(signo, code, env->pc);
| ^
../bsd-user/riscv/target_arch_cpu.h:129:9: error: call to undeclared
function 'process_pending_signals'; ISO C99 and later do not support
implicit function declarations
[-Werror,-Wimplicit-function-declaration]
129 | process_pending_signals(env);
| ^
../bsd-user/main.c:608:5: error: call to undeclared function
'signal_init'; ISO C99 and later do not support implicit function
declarations [-Werror,-Wimplicit-function-declaration]
608 | signal_init();
| ^
3 errors generated.
thanks
-- PMM
next prev parent reply other threads:[~2024-09-13 10:38 UTC|newest]
Thread overview: 56+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-09-12 5:29 [PULL 00/47] riscv-to-apply queue Alistair Francis
2024-09-12 5:29 ` [PULL 01/47] target/riscv: Add a property to set vl to ceil(AVL/2) Alistair Francis
2024-09-12 5:29 ` [PULL 02/47] tests/acpi: Add empty ACPI SRAT data file for RISC-V Alistair Francis
2024-09-12 5:29 ` [PULL 03/47] tests/qtest/bios-tables-test.c: Enable numamem testing " Alistair Francis
2024-09-12 5:29 ` [PULL 04/47] tests/acpi: Add expected ACPI SRAT AML file " Alistair Francis
2024-09-12 5:29 ` [PULL 05/47] target/riscv/tcg/tcg-cpu.c: consider MISA bit choice in implied rule Alistair Francis
2024-09-12 5:29 ` [PULL 06/47] target/riscv: fix za64rs enabling Alistair Francis
2024-09-12 5:29 ` [PULL 07/47] target: riscv: Enable Bit Manip for OpenTitan Ibex CPU Alistair Francis
2024-09-12 5:29 ` [PULL 08/47] target/riscv/kvm: Fix the group bit setting of AIA Alistair Francis
2024-09-12 5:29 ` [PULL 09/47] target/riscv: Stop timer with infinite timecmp Alistair Francis
2024-09-12 5:29 ` [PULL 10/47] target/riscv/cpu.c: Add 'fcsr' register to QEMU log as a part of F extension Alistair Francis
2024-09-12 5:29 ` [PULL 11/47] util/util/cpuinfo-riscv.c: fix riscv64 build on musl libc Alistair Francis
2024-09-12 5:29 ` [PULL 12/47] target/riscv: Preliminary textra trigger CSR writting support Alistair Francis
2024-09-12 5:29 ` [PULL 13/47] target/riscv: Add textra matching condition for the triggers Alistair Francis
2024-09-12 5:29 ` [PULL 14/47] exec/memtxattr: add process identifier to the transaction attributes Alistair Francis
2024-09-12 5:29 ` [PULL 15/47] hw/riscv: add riscv-iommu-bits.h Alistair Francis
2024-09-12 5:29 ` [PULL 16/47] hw/riscv: add RISC-V IOMMU base emulation Alistair Francis
2024-09-12 5:29 ` [PULL 17/47] pci-ids.rst: add Red Hat pci-id for RISC-V IOMMU device Alistair Francis
2024-09-12 5:29 ` [PULL 18/47] hw/riscv: add riscv-iommu-pci reference device Alistair Francis
2024-09-12 5:29 ` [PULL 19/47] hw/riscv/virt.c: support for RISC-V IOMMU PCIDevice hotplug Alistair Francis
2024-09-12 5:29 ` [PULL 20/47] test/qtest: add riscv-iommu-pci tests Alistair Francis
2024-09-12 5:29 ` [PULL 21/47] hw/riscv/riscv-iommu: add Address Translation Cache (IOATC) Alistair Francis
2024-09-12 5:29 ` [PULL 22/47] hw/riscv/riscv-iommu: add ATS support Alistair Francis
2024-09-12 5:29 ` [PULL 23/47] hw/riscv/riscv-iommu: add DBG support Alistair Francis
2024-09-12 5:29 ` [PULL 24/47] qtest/riscv-iommu-test: add init queues test Alistair Francis
2024-09-12 5:29 ` [PULL 25/47] docs/specs: add riscv-iommu Alistair Francis
2024-09-12 5:29 ` [PULL 26/47] bsd-user: Implement RISC-V CPU initialization and main loop Alistair Francis
2024-09-12 5:29 ` [PULL 27/47] bsd-user: Add RISC-V CPU execution loop and syscall handling Alistair Francis
2024-09-15 19:49 ` Daniel Henrique Barboza
2024-09-12 5:29 ` [PULL 28/47] bsd-user: Implement RISC-V CPU register cloning and reset functions Alistair Francis
2024-09-12 5:29 ` [PULL 29/47] bsd-user: Implement RISC-V TLS register setup Alistair Francis
2024-09-12 5:29 ` [PULL 30/47] bsd-user: Add RISC-V ELF definitions and hardware capability detection Alistair Francis
2024-09-12 5:29 ` [PULL 31/47] bsd-user: Define RISC-V register structures and register copying Alistair Francis
2024-09-12 5:29 ` [PULL 32/47] bsd-user: Add RISC-V signal trampoline setup function Alistair Francis
2024-09-15 19:51 ` Daniel Henrique Barboza
2024-09-16 6:13 ` Ajeet Singh
2024-09-12 5:29 ` [PULL 33/47] bsd-user: Implement RISC-V sysarch system call emulation Alistair Francis
2024-09-12 5:29 ` [PULL 34/47] bsd-user: Add RISC-V thread setup and initialization support Alistair Francis
2024-09-12 5:29 ` [PULL 35/47] bsd-user: Define RISC-V VM parameters and helper functions Alistair Francis
2024-09-12 5:29 ` [PULL 36/47] bsd-user: Define RISC-V system call structures and constants Alistair Francis
2024-09-12 5:29 ` [PULL 37/47] bsd-user: Add generic RISC-V64 target definitions Alistair Francis
2024-09-12 5:29 ` [PULL 38/47] bsd-user: Define RISC-V signal handling structures and constants Alistair Francis
2024-09-12 5:29 ` [PULL 39/47] bsd-user: Implement RISC-V signal trampoline setup functions Alistair Francis
2024-09-12 5:29 ` [PULL 40/47] bsd-user: Implement 'get_mcontext' for RISC-V Alistair Francis
2024-09-12 5:29 ` [PULL 41/47] bsd-user: Implement set_mcontext and get_ucontext_sigreturn for RISCV Alistair Francis
2024-09-12 5:29 ` [PULL 42/47] bsd-user: Add RISC-V 64-bit Target Configuration and Debug XML Files Alistair Francis
2024-09-12 5:29 ` [PULL 43/47] hw/riscv: Respect firmware ELF entry point Alistair Francis
2024-09-12 5:29 ` [PULL 44/47] target: riscv: Add Svvptc extension support Alistair Francis
2024-09-12 5:29 ` [PULL 45/47] target/riscv32: Fix masking of physical address Alistair Francis
2024-09-12 5:29 ` [PULL 46/47] target/riscv/cpu_helper: Fix linking problem with semihosting disabled Alistair Francis
2024-09-12 5:29 ` [PULL 47/47] hw/intc: riscv-imsic: Fix interrupt state updates Alistair Francis
2024-09-13 10:37 ` Peter Maydell [this message]
2024-09-14 9:15 ` [PULL 00/47] riscv-to-apply queue Alistair Francis
2024-09-15 19:58 ` Daniel Henrique Barboza
2024-09-16 6:12 ` Thomas Huth
2024-09-16 10:43 ` Daniel Henrique Barboza
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