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From: Peter Maydell <peter.maydell@linaro.org>
To: Richard Henderson <richard.henderson@linaro.org>
Cc: QEMU Developers <qemu-devel@nongnu.org>, qemu-arm <qemu-arm@nongnu.org>
Subject: Re: [Qemu-devel] [PATCH v3 2/5] target/arm: Fill in ARMISARegisters for kvm64
Date: Mon, 12 Nov 2018 11:37:50 +0000	[thread overview]
Message-ID: <CAFEAcA_WJMAsHWx+OTO+j0eTsHodpXkyxLv6cAdXxgjsCmTYhw@mail.gmail.com> (raw)
In-Reply-To: <20181108175246.13416-3-richard.henderson@linaro.org>

On 8 November 2018 at 17:52, Richard Henderson
<richard.henderson@linaro.org> wrote:
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---

>      /* Old kernels may not know about the PREFERRED_TARGET ioctl: however
>       * we know these will only support creating one kind of guest CPU,
>       * which is its preferred CPU type. Fortunately these old kernels
> @@ -474,8 +497,71 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
>      ahcf->target = init.target;
>      ahcf->dtb_compatible = "arm,arm-v8";
>
> +    err = read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64pfr0,
> +                         ARM64_SYS_REG(3, 0, 0, 4, 0));
> +    if (unlikely(err < 0)) {
> +        /*
> +         * Before v4.15, the kernel only exposed a limited number of system
> +         * registers, not including any of the interesting AArch64 ID regs.
> +         * For the most part we could leave these fields as zero with minimal
> +         * effect, since this does not affect the values seen by the guest.

These older kernels do implement reading of id_isar0 through
id_isar5, though -- we could read and use those values rather than
leaving them zero.

> +         *
> +         * However, it could cause problems down the line for QEMU,
> +         * so provide a minimal v8.0 default.
> +         *
> +         * ??? Could read MIDR and use knowledge from cpu64.c.
> +         * ??? Could map a page of memory into our temp guest and
> +         *     run the tiniest of hand-crafted kernels to extract
> +         *     the values seen by the guest.
> +         * ??? Either of these sounds like too much effort just
> +         *     to work around running a modern host kernel.
> +         */
> +        ahcf->isar.id_aa64pfr0 = 0x00000011; /* EL1&0, AArch64 only */
> +        err = 0;

Doesn't this code path leave everything except id_aa64pfr0 as
zero, thus leaving us with the "could cause problems down the
line" situation ?

thanks
-- PMM

  reply	other threads:[~2018-11-12 11:38 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-11-08 17:52 [Qemu-devel] [PATCH v3 0/5] target/arm: KVM vs ARMISARegisters Richard Henderson
2018-11-08 17:52 ` [Qemu-devel] [PATCH v3 1/5] target/arm: Install ARMISARegisters from kvm host Richard Henderson
2018-11-08 17:52 ` [Qemu-devel] [PATCH v3 2/5] target/arm: Fill in ARMISARegisters for kvm64 Richard Henderson
2018-11-12 11:37   ` Peter Maydell [this message]
2018-11-12 14:09     ` Richard Henderson
2018-11-12 14:34       ` Peter Maydell
2018-11-12 16:00         ` Richard Henderson
2018-11-08 17:52 ` [Qemu-devel] [PATCH v3 3/5] target/arm: Introduce read_sys_reg32 for kvm32 Richard Henderson
2018-11-08 17:52 ` [Qemu-devel] [PATCH v3 4/5] target/arm: Fill in ARMISARegisters " Richard Henderson
2018-11-12 11:39   ` Peter Maydell
2018-11-12 12:42   ` Peter Maydell
2018-11-12 14:10     ` Richard Henderson
2018-11-08 17:52 ` [Qemu-devel] [PATCH v3 5/5] target/arm: Convert t32ee from feature bit to isar3 test Richard Henderson
2018-11-11 23:44   ` [Qemu-devel] [Qemu-arm] " Philippe Mathieu-Daudé

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