From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37271) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z3Qhn-0000kY-F5 for qemu-devel@nongnu.org; Fri, 12 Jun 2015 11:17:16 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Z3Qhi-0006LI-K5 for qemu-devel@nongnu.org; Fri, 12 Jun 2015 11:17:15 -0400 Received: from mail-vn0-f46.google.com ([209.85.216.46]:33366) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z3Qhi-0006LC-G4 for qemu-devel@nongnu.org; Fri, 12 Jun 2015 11:17:10 -0400 Received: by vnbf190 with SMTP id f190so6500663vnb.0 for ; Fri, 12 Jun 2015 08:17:10 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: <02f601d0a1e6$90c7d630$b2578290$@samsung.com> References: <02f601d0a1e6$90c7d630$b2578290$@samsung.com> From: Peter Maydell Date: Fri, 12 Jun 2015 16:16:49 +0100 Message-ID: Content-Type: text/plain; charset=UTF-8 Subject: Re: [Qemu-devel] [PATCH v4] Use Aff1 with mpidr List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Pavel Fedin Cc: Shlomo Pongratz , Shlomo Pongratz , QEMU Developers On 8 June 2015 at 13:28, Pavel Fedin wrote: > +extern int arm_cpus_per_cluster; > + > #define TYPE_AARCH64_CPU "aarch64-cpu" > #define AARCH64_CPU_CLASS(klass) \ > OBJECT_CLASS_CHECK(AArch64CPUClass, (klass), TYPE_AARCH64_CPU) > diff --git a/target-arm/cpu.c b/target-arm/cpu.c > index 4a888ab..fa9f1c0 100644 > --- a/target-arm/cpu.c > +++ b/target-arm/cpu.c > @@ -383,17 +383,29 @@ static inline void unset_feature(CPUARMState *env, int feature) > env->features &= ~(1ULL << feature); > } > > +int arm_cpus_per_cluster = 8; This doesn't need to be global, it doesn't need to be exposed in a header file, and it definitely doesn't need to be non-constant. I suggest #define ARM_CPUS_PER_CLUSTER 8 > + > static void arm_cpu_initfn(Object *obj) > { > CPUState *cs = CPU(obj); > ARMCPU *cpu = ARM_CPU(obj); > static bool inited; > + uint32_t Aff1, Aff0; > > cs->env_ptr = &cpu->env; > cpu_exec_init(&cpu->env); > cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal, > g_free, g_free); > > + /* > + * We don't support setting cluster ID ([16..23]) (known as Aff2 > + * in later ARM ARM versions), or any of the higher affinity level fields, > + * so these bits always RAZ. > + */ > + Aff1 = cs->cpu_index / arm_cpus_per_cluster; > + Aff0 = cs->cpu_index % arm_cpus_per_cluster; > + cpu->mp_affinity = (Aff1 << 8) | Aff0; Worth also mentioning in the comment that KVM will override this. These are minor nits so I plan to just fix them as I apply this to target-arm.next, unless you object. thanks -- PMM