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bh=Q04MB9sbtDquxr5tfECR0Pc+WkFOv2d45d7auHnPkmA=; b=p1o5t6tzL/cCEpnLEl+ublgrgLLjVnvmUzgBg2h2Aq0bGj2qz7zHrHIXnS099UwBzk KCpHlm9fkC1+FDlMtPQHht+GBCjAWtkin0zCrm+2py2YojHsX2aP2j16/oXvZ65piFlz UAJhyaSNrGpVkg6idCsPptqC4dYmiGV5bRIAn49bNXA3n/vc0fAaEorJLxgQRwMuahOu e5eV1ZJ59uxDZoxfXm4V89/StOgDV7ef/8yP5um8GiibYRWPgNZCVE371aTBdefbxEri TlJYfcfMwRgheB6vPCtg8Ndtn3LrKuYZ6MlKLNLcbOWnclVzHoBshLMH7x74yPioEW6D 82AQ== X-Forwarded-Encrypted: i=1; AJvYcCXDpQmWczGVDDwgWyTuycyxDfwIThjdBrr/61gFEPa4Fq8/PYsqOBGRSJPKKjjHFRvG2Lr3/WPKaP+hzuY//M9jlfuQWQs= X-Gm-Message-State: AOJu0YzAcRCue6n2/RXM2GWnyPNeWtlNvBcx4s416b9bLNbkhC5D/1J5 Y/WBgJfers/AzXx4zBib4YsIYakOwTracFTBQyLuj2qwBoCEgKOM3GCXtasmXSur0qD5jP9ooRj AGQSpqLkc0qViRgs/9XAjKKSpPI4YeY1FfYMAUg== X-Google-Smtp-Source: AGHT+IHETg+DW7wEI7VIwC7RZgtjWqUJ1WfHhbJqO41hWKlSkU9VDL75XLotl9HvCb3CcX5971nuZYoChWpujPSYYXU= X-Received: by 2002:ac2:5f49:0:b0:513:ba98:36a with SMTP id 9-20020ac25f49000000b00513ba98036amr10290422lfz.10.1712144984208; Wed, 03 Apr 2024 04:49:44 -0700 (PDT) MIME-Version: 1.0 References: <20240330103128.3185962-1-ruanjinjie@huawei.com> <20240330103128.3185962-19-ruanjinjie@huawei.com> <6ff19301-8791-384e-bd40-5f58058f4234@huawei.com> In-Reply-To: <6ff19301-8791-384e-bd40-5f58058f4234@huawei.com> From: Peter Maydell Date: Wed, 3 Apr 2024 12:49:32 +0100 Message-ID: Subject: Re: [PATCH v11 18/23] hw/intc/arm_gicv3: Handle icv_nmiar1_read() for icc_nmiar1_read() To: Jinjie Ruan Cc: eduardo@habkost.net, marcel.apfelbaum@gmail.com, philmd@linaro.org, wangyanan55@huawei.com, richard.henderson@linaro.org, qemu-devel@nongnu.org, qemu-arm@nongnu.org Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::131; envelope-from=peter.maydell@linaro.org; helo=mail-lf1-x131.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Wed, 3 Apr 2024 at 04:16, Jinjie Ruan wrote: > On 2024/4/3 0:12, Peter Maydell wrote: > >> @@ -776,7 +811,11 @@ static uint64_t icv_iar_read(CPUARMState *env, const ARMCPRegInfo *ri) > >> if (thisgrp == grp && icv_hppi_can_preempt(cs, lr)) { > >> intid = ich_lr_vintid(lr); > >> if (!gicv3_intid_is_special(intid)) { > >> - icv_activate_irq(cs, idx, grp); > >> + if (!(lr & ICH_LR_EL2_NMI)) { > > > > This is missing checks on both whether the GIC has NMI support and > > on whether the SCTLR NMI bit is set (compare pseudocode > > VirtualReadIAR1()). I suggest defining a > > > > bool nmi = cs->gic->nmi_support && > > (env->cp15.sctlr_el[arm_current_el(env)] & SCTLR_NMI) && > > (lr & ICH_LR_EL2_NMI); > > The nmi_support check is redundant, as if FEAT_GICv3_NMI is unsupported, > the ICH_LR_EL2.NMI is RES0, so if ICH_LR_EL2.NMI is 1, FEAT_GICv3_NMI > has been surely realized. As far as I can see you haven't changed ich_lr_write() to enforce that, though, so the guest can write 1 to the NMI bit even if the GIC doesn't support FEAT_GICv3_NMI. If you want to skip checking nmi_support here you need to enforce that the NMI bit in the LR is 0 in ich_lr_write(). thanks -- PMM