Re: [PATCH] target/arm: fix MPIDR value for ARM CPUs with SMT

[Peter Maydell <peter.maydell@linaro.org>]

On Thu, 2 May 2024 at 14:11, Marcin Juszkiewicz
<marcin.juszkiewicz@linaro.org> wrote:
>
> W dniu 2.05.2024 o 15:04, Dorjoy Chowdhury pisze:
> >> Should "return" also have "(1 << 24) |" to have MT=1 set?
> >>
> >> Otherwise MPIDR_EL1 = 0x000100 can mean core0 in cluster1 or core1 in
> >> cluster0.
> >>
> >> Value 0x1000100 shows MT=1 so thread0 in core1 in cluster0.
>
> > I don't know all the details but from what I understand the
> > "arm_build_mp_afiinity" is used to set the "mp_affinity" member
> > variable which I assume is about affinity, not the whole MPIDR
> > register value. That is what I assumed because the Uniprocessor
> > indication bit(30) is being set only in the "mpidr_read_val" function.
> > In the patch, the MT bit is also being set in the "mpidr_read_val"
> > function based on the SMT status (has_smt) of the CPU.
>
> mpidr_read_val() is used only to set VMPIDR and VMPIDR_EL2 registers.
>
> So setting MT bit for MPIDR_EL1 needs to be added somewhere.

The readfn for MPIDR_EL1 is mpidr_read(), which calls
mpidr_read_val().

thanks
-- PMM