From: Peter Maydell <peter.maydell@linaro.org>
To: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: "Richard Henderson" <richard.henderson@linaro.org>,
"Jørgen Hansen" <Jorgen.Hansen@wdc.com>,
"Ajay Joshi" <Ajay.Joshi@wdc.com>,
qemu-devel <qemu-devel@nongnu.org>,
"Sid Manning" <sidneym@quicinc.com>
Subject: Re: An issue with x86 tcg and MMIO
Date: Thu, 2 Feb 2023 13:31:02 +0000 [thread overview]
Message-ID: <CAFEAcA_b0TeXcGyNuELBe3c4QzVRr8OPpDGunprhfkZ3L3bEVg@mail.gmail.com> (raw)
In-Reply-To: <20230202123118.00003bd6@Huawei.com>
On Thu, 2 Feb 2023 at 12:31, Jonathan Cameron
<Jonathan.Cameron@huawei.com> wrote:
>
> On Thu, 2 Feb 2023 11:39:28 +0000
> Peter Maydell <peter.maydell@linaro.org> wrote:
> > You might want to look at whether QEMU's iommu functionality is helpful
> > to you -- I'm assuming CXL doesn't do weird stuff on a less-than-page
> > granularity, and the iommu APIs will let you do "programmatically decide
> > where this address should actually go". The other option involves
> > mapping and unmapping MemoryRegions inside a container MR.
>
> Unfortunately it does weird stuff well below a page granularity.
> Interleaving is down to 256 bytes.
That's unfortunate...
At any rate, conceptually we ought to be able to execute from
an instruction that overlaps between actual-RAM and an MMIO
MemoryRegion; it would be nice if we could fall back to the
execute-and-discard approach for that in the same way as if
the entire insn was in MMIO.
-- PMM
prev parent reply other threads:[~2023-02-02 13:31 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <78bc53e3-bad3-a5c3-9e53-7a89054aa37a@wdc.com>
2023-02-01 21:50 ` An issue with x86 tcg and MMIO Richard Henderson
2023-02-02 9:39 ` Jonathan Cameron via
2023-02-02 10:56 ` Richard Henderson
2023-02-02 11:39 ` Peter Maydell
2023-02-02 12:31 ` Jonathan Cameron via
2023-02-02 13:31 ` Peter Maydell [this message]
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