From: Peter Maydell <peter.maydell@linaro.org>
To: Christopher Covington <cov@codeaurora.org>
Cc: Chengyu Song <csong84@gatech.edu>,
QEMU Developers <qemu-devel@nongnu.org>
Subject: Re: [Qemu-devel] [PATCH] ARM64: support access to more performance registers in AA64 mode
Date: Wed, 3 Dec 2014 20:45:04 +0000 [thread overview]
Message-ID: <CAFEAcA_bwD-mbLjteneXiUbX0xiUe_Hr_iXGcVB-u9BEHr8XpQ@mail.gmail.com> (raw)
In-Reply-To: <547F71B0.4030801@codeaurora.org>
On 3 December 2014 at 20:25, Christopher Covington <cov@codeaurora.org> wrote:
> Hi Chengyu,
>
> On 12/03/2014 02:12 AM, Chengyu Song wrote:
>> { .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1,
>> .access = PL1_RW,
>> .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
>> .resetvalue = 0,
>> .writefn = pmintenset_write, .raw_writefn = raw_write },
>> + { .name = "PMINTENSET_EL1", .state = ARM_CP_STATE_AA64,
>> + .opc0 = 3, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1,
>> + .access = PL1_RW,
>> + .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
>> + .resetvalue = 0,
>> + .writefn = pmintenset_write, .raw_writefn = raw_write },
>
> Again, should .type = ARM_CP_NO_MIGRATE be used as this shares a variable with
> PMINTSET?
I think in this case and PMINTENCLR you can actually share a
single STATE_BOTH regdef, since the crn/crm/opc encodings
line up. Generally we prefer to do that where it works out.
thanks
-- PMM
next prev parent reply other threads:[~2014-12-03 20:45 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-12-03 7:12 [Qemu-devel] [PATCH] ARM64: support access to more performance registers in AA64 mode Chengyu Song
2014-12-03 20:25 ` Christopher Covington
2014-12-03 20:45 ` Peter Maydell [this message]
2014-12-03 20:53 ` Chengyu Song
2014-12-03 21:12 ` Peter Maydell
2014-12-06 21:07 ` Chengyu Song
2014-12-06 21:11 ` Chengyu Song
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