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From: Peter Maydell <peter.maydell@linaro.org>
To: Palmer Dabbelt <palmer@sifive.com>
Cc: "open list:RISC-V" <qemu-riscv@nongnu.org>,
	QEMU Developers <qemu-devel@nongnu.org>
Subject: Re: [Qemu-devel] [PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 1, v3
Date: Thu, 19 Sep 2019 13:26:56 +0100	[thread overview]
Message-ID: <CAFEAcA_h3+Zm=PXiGV7THCL0wJz_RyWEjfCrSJV2exWOZQ0Dig@mail.gmail.com> (raw)
In-Reply-To: <20190918145640.17349-1-palmer@sifive.com>

On Wed, 18 Sep 2019 at 16:27, Palmer Dabbelt <palmer@sifive.com> wrote:
>
> The following changes since commit f8c3db33a5e863291182f8862ddf81618a7c6194:
>
>   target/sparc: Switch to do_transaction_failed() hook (2019-09-17 12:01:00 +0100)
>
> are available in the Git repository at:
>
>   git://github.com/palmer-dabbelt/qemu.git tags/riscv-for-master-4.2-sf1-v3
>
> for you to fetch changes up to b3e86929189c526d22ef49e18f2f5066535f6deb:
>
>   gdbstub: riscv: fix the fflags registers (2019-09-17 08:42:50 -0700)
>
> ----------------------------------------------------------------
> RISC-V Patches for the 4.2 Soft Freeze, Part 1, v3
>
> This contains quite a few patches that I'd like to target for 4.2.
> They're mostly emulation fixes for the sifive_u board, which now much
> more closely matches the hardware and can therefor run the same fireware
> as what gets loaded onto the board.  Additional user-visible
> improvements include:
>
> * support for loading initrd files from the command line into Linux, via
>   /chosen/linux,initrd-{start,end} device tree nodes.
> * The conversion of LOG_TRACE to trace events.
> * The addition of clock DT nodes for our uart and ethernet.
>
> This also includes some preliminary work for the H extension patches,
> but does not include the H extension patches as I haven't had time to
> review them yet.
>
> This passes my OE boot test on 32-bit and 64-bit virt machines, as well
> as a 64-bit upstream Linux boot on the sifive_u machine.  It has been
> fixed to actually pass "make check" this time.
>
> Changes since v2 (never made it to the list):
>
> * Sets the sifive_u machine default core count to 2 instead of 5.
>
> Changes since v1 <20190910190513.21160-1-palmer@sifive.com>:
>
> * Sets the sifive_u machine default core count to 5 instead of 1, as
>   it's impossible to have a single core sifive_u machine.
>


Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/4.2
for any user-visible changes.

-- PMM


      parent reply	other threads:[~2019-09-19 12:29 UTC|newest]

Thread overview: 52+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-09-18 14:55 [Qemu-devel] [PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 1, v3 Palmer Dabbelt
2019-09-18 14:55 ` [Qemu-devel] [PULL 01/48] riscv: sifive_u: Add support for loading initrd Palmer Dabbelt
2019-09-18 14:55 ` [Qemu-devel] [PULL 02/48] riscv: sivive_u: Add dummy serial clock and aliases entry for uart Palmer Dabbelt
2019-09-18 14:55 ` [Qemu-devel] [PULL 03/48] riscv: sifive_u: Fix clock-names property for ethernet node Palmer Dabbelt
2019-09-18 14:55 ` [Qemu-devel] [PULL 04/48] target/riscv/pmp: Restrict priviledged PMP to system-mode emulation Palmer Dabbelt
2019-09-18 14:55 ` [Qemu-devel] [PULL 05/48] target/riscv/pmp: Convert qemu_log_mask(LOG_TRACE) to trace events Palmer Dabbelt
2019-09-18 14:55 ` [Qemu-devel] [PULL 06/48] riscv: plic: Remove unused interrupt functions Palmer Dabbelt
2019-09-18 14:55 ` [Qemu-devel] [PULL 07/48] target/riscv: Create function to test if FP is enabled Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-devel] [PULL 08/48] target/riscv: Update the Hypervisor CSRs to v0.4 Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-devel] [PULL 09/48] riscv: rv32: Root page table address can be larger than 32-bit Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-devel] [PULL 10/48] riscv: Add a helper routine for finding firmware Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-devel] [PULL 11/48] riscv: Resolve full path of the given bios image Palmer Dabbelt
2019-09-24 10:17   ` Peter Maydell
2019-10-02 21:38     ` Alistair Francis
2019-09-18 14:56 ` [Qemu-devel] [PULL 12/48] riscv: hmp: Add a command to show virtual memory mappings Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-devel] [PULL 13/48] riscv: sifive_test: Add reset functionality Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-devel] [PULL 14/48] riscv: hw: Remove duplicated "hw/hw.h" inclusion Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-devel] [PULL 15/48] riscv: hw: Remove superfluous "linux, phandle" property Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-devel] [PULL 16/48] riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-devel] [PULL 17/48] riscv: hw: Remove not needed PLIC properties in device tree Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-devel] [PULL 18/48] riscv: hw: Change create_fdt() to return void Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-devel] [PULL 19/48] riscv: hw: Change to use qemu_log_mask(LOG_GUEST_ERROR, ...) instead Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-devel] [PULL 20/48] riscv: hw: Remove the unnecessary include of target/riscv/cpu.h Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-devel] [PULL 21/48] riscv: roms: Remove executable attribute of opensbi images Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-devel] [PULL 22/48] riscv: sifive_u: Remove the unnecessary include of prci header Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-devel] [PULL 23/48] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h} Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-devel] [PULL 24/48] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-devel] [PULL 25/48] riscv: sifive_e: prci: Update the PRCI register block size Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-devel] [PULL 26/48] riscv: sifive_e: Drop sifive_mmio_emulate() Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-devel] [PULL 27/48] riscv: Add a sifive_cpu.h to include both E and U cpu type defines Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-devel] [PULL 28/48] riscv: hart: Extract hart realize to a separate routine Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-devel] [PULL 29/48] riscv: hart: Add a "hartid-base" property to RISC-V hart array Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-devel] [PULL 30/48] riscv: sifive_u: Set the minimum number of cpus to 2 Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-devel] [PULL 31/48] riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-devel] [PULL 32/48] riscv: sifive_u: Update PLIC hart topology configuration string Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-devel] [PULL 33/48] riscv: sifive: Implement PRCI model for FU540 Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-devel] [PULL 34/48] riscv: sifive_u: Generate hfclk and rtcclk nodes Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-devel] [PULL 35/48] riscv: sifive_u: Add PRCI block to the SoC Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-devel] [PULL 36/48] riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-devel] [PULL 37/48] riscv: sifive_u: Update UART base addresses and IRQs Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-devel] [PULL 38/48] riscv: sifive_u: Change UART node name in device tree Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-devel] [PULL 39/48] riscv: roms: Update default bios for sifive_u machine Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-devel] [PULL 40/48] riscv: sifive: Implement a model for SiFive FU540 OTP Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-devel] [PULL 41/48] riscv: sifive_u: Instantiate OTP memory with a serial number Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-devel] [PULL 42/48] riscv: sifive_u: Fix broken GEM support Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-devel] [PULL 43/48] riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernet Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-devel] [PULL 44/48] riscv: sifive_u: Update model and compatible strings in device tree Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-devel] [PULL 45/48] target/riscv: Use both register name and ABI name Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-devel] [PULL 46/48] target/riscv: Fix mstatus dirty mask Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-devel] [PULL 47/48] target/riscv: Use TB_FLAGS_MSTATUS_FS for floating point Palmer Dabbelt
2019-09-18 14:56 ` [Qemu-devel] [PULL 48/48] gdbstub: riscv: fix the fflags registers Palmer Dabbelt
2019-09-19 12:26 ` Peter Maydell [this message]

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