From: Peter Maydell <peter.maydell@linaro.org>
To: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
Cc: "QEMU Developers" <qemu-devel@nongnu.org>,
qemu-arm <qemu-arm@nongnu.org>,
"Richard Henderson" <richard.henderson@linaro.org>,
"KONRAD Frederic" <frederic.konrad@adacore.com>,
"Alistair Francis" <alistair@alistair23.me>,
"Philippe Mathieu-Daudé" <philmd@redhat.com>,
"Francisco Iglesias" <frasse.iglesias@gmail.com>,
figlesia@xilinx.com,
"Stefano Stabellini" <sstabellini@kernel.org>,
"Sai Pavan Boddu" <sai.pavan.boddu@xilinx.com>,
"Edgar Iglesias" <edgar.iglesias@xilinx.com>
Subject: Re: [Qemu-devel] [PATCH v4 0/4] arm: Add first models of Xilinx Versal SoC
Date: Mon, 29 Oct 2018 14:21:31 +0000 [thread overview]
Message-ID: <CAFEAcA_i0MHixDocr95Dhedj1jqHxA7JPg_1qbW+eAK8qQefcg@mail.gmail.com> (raw)
In-Reply-To: <20181022173559.17111-1-edgar.iglesias@gmail.com>
On 22 October 2018 at 18:35, Edgar E. Iglesias <edgar.iglesias@gmail.com> wrote:
> From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
>
> This patch series adds initial support for Xilinx's Versal SoC.
> Xilinx is introducing Versal, an adaptive compute acceleration platform
> (ACAP), built on 7nm FinFET process technology. Versal ACAPs combine Scalar
> Processing Engines, Adaptable Hardware Engines, and Intelligent Engines with
> leading-edge memory and interfacing technologies to deliver powerful
> heterogeneous acceleration for any application. The Versal AI Core series has
> five devices, offering 128 to 400 AI Engines. The series includes dual-core Arm
> Cortex-A72 application processors, dual-core Arm Cortex-R5 real-time
> processors, 256KB of on-chip memory with ECC, more than 1,900 DSP engines
> optimized for high-precision floating point with low latency.
>
> More info can be found here:
> https://www.xilinx.com/news/press/2018/xilinx-unveils-versal-the-first-in-a-new-category-of-platforms-delivering-rapid-innovation-with-software-programmability-and-scalable-ai-inference.html
>
>
> In QEMU we'd like to have a virtual developer board with the Versal SoC
> and a selected set of peripherals under the control of QEMU.
> We'd like to gradually extend this board as QEMU gains more support
> for Versal hardware components. QEMU will generate a device-tree
> describing only the components it supports and includes in the virtual
> dev board.
>
> Before adding Versal support, this series starts with a few fixes to the
> GEM that I ran into when running recent kernels on the Versal and ZynqMP
> models.
>
> I also noticed a problem with HVC insns not being enabled when using
> QEMU's PSCI implementation on CPU's with EL2 and EL3 enabled. This causes
> problems for Linux/KVM guests, also fixed in this series.
Applied patches 3 and 4 to target-arm.next (1 and 2 being already
in master), thanks.
-- PMM
prev parent reply other threads:[~2018-10-29 14:21 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-10-22 17:35 [Qemu-devel] [PATCH v4 0/4] arm: Add first models of Xilinx Versal SoC Edgar E. Iglesias
2018-10-22 17:35 ` [Qemu-devel] [PATCH v4 1/4] net: cadence_gem: Announce availability of priority queues Edgar E. Iglesias
2018-10-22 17:35 ` [Qemu-devel] [PATCH v4 2/4] net: cadence_gem: Announce 64bit addressing support Edgar E. Iglesias
2018-10-22 17:35 ` [Qemu-devel] [PATCH v4 3/4] hw/arm: versal: Add a model of Xilinx Versal SoC Edgar E. Iglesias
2018-10-22 17:35 ` [Qemu-devel] [PATCH v4 4/4] hw/arm: versal: Add a virtual Xilinx Versal board Edgar E. Iglesias
2018-10-30 13:31 ` Peter Maydell
2018-11-02 11:33 ` Edgar E. Iglesias
2018-10-29 14:21 ` Peter Maydell [this message]
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