From: Peter Maydell <peter.maydell@linaro.org>
To: Richard Henderson <richard.henderson@linaro.org>
Cc: QEMU Developers <qemu-devel@nongnu.org>
Subject: Re: [Qemu-devel] [PATCH v2] target/arm: Vectorize USHL and SSHL
Date: Fri, 7 Jun 2019 16:44:18 +0100 [thread overview]
Message-ID: <CAFEAcA_kL1WCtSCHp_h1F4Ch6qU6tYXuvqUQhqxGoeHiqApyNQ@mail.gmail.com> (raw)
In-Reply-To: <0a55f185-fb9f-335f-2342-9c214706a4d1@linaro.org>
On Fri, 7 Jun 2019 at 16:40, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> On 6/7/19 9:54 AM, Peter Maydell wrote:
> > On Tue, 4 Jun 2019 at 00:22, Richard Henderson
> > <richard.henderson@linaro.org> wrote:
> >>
> >> These instructions shift left or right depending on the sign
> >> of the input, and 7 bits are significant to the shift. This
> >> requires several masks and selects in addition to the actual
> >> shifts to form the complete answer.
> >>
> >> That said, the operation is still a small improvement even for
> >> two 64-bit elements -- 13 vector operations instead of 2 * 7
> >> integer operations.
> >>
> >> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> >> ---
> >
> > Applied to target-arm.next, thanks.
> >
> > NB: in v1 this series had a second patch. I'm assuming you
> > dropped it deliberately -- if not, let me know.
>
> Oops, no. Can you please grab it with your r-b from v1?
Sure.
-- PMM
prev parent reply other threads:[~2019-06-07 17:54 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-03 23:22 [Qemu-devel] [PATCH v2] target/arm: Vectorize USHL and SSHL Richard Henderson
2019-06-04 2:54 ` no-reply
2019-06-07 14:54 ` Peter Maydell
2019-06-07 15:40 ` Richard Henderson
2019-06-07 15:44 ` Peter Maydell [this message]
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