From: Peter Maydell <peter.maydell@linaro.org>
To: Gustavo Romero <gustavo.romero@linaro.org>
Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org,
richard.henderson@linaro.org, alex.bennee@linaro.org
Subject: Re: [PATCH v10 2/3] target/arm: Implement FEAT_MEC registers
Date: Tue, 7 Oct 2025 15:32:57 +0100 [thread overview]
Message-ID: <CAFEAcA_mBh2GeDMXG5b2GAbNj85z8g7bZicxdiyH6jogndDHpw@mail.gmail.com> (raw)
In-Reply-To: <20251006001018.219756-3-gustavo.romero@linaro.org>
On Mon, 6 Oct 2025 at 01:10, Gustavo Romero <gustavo.romero@linaro.org> wrote:
>
> Add all FEAT_MEC registers. Enable access to the registers via the
> SCTLR2 and TCR2 control bits. Add the two new cache management
> instructions, which are nops in QEMU because we do not model caches.
>
> Message-ID: <20250711140828.1714666-3-gustavo.romero@linaro.org>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> [rth: Squash 3 patches to add all registers at once.]
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: Gustavo Romero <gustavo.romero@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
next prev parent reply other threads:[~2025-10-07 14:34 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-06 0:10 [PATCH v10 0/3] target/arm: Add FEAT_MEC to max cpu Gustavo Romero
2025-10-06 0:10 ` [PATCH v10 1/3] target/arm: Add a cpreg flag to indicate no trap in NV Gustavo Romero
2025-10-07 14:31 ` Peter Maydell
2025-10-06 0:10 ` [PATCH v10 2/3] target/arm: Implement FEAT_MEC registers Gustavo Romero
2025-10-07 14:32 ` Peter Maydell [this message]
2025-10-06 0:10 ` [PATCH v10 3/3] target/arm: Enable FEAT_MEC in -cpu max Gustavo Romero
2025-10-07 14:34 ` Peter Maydell
2025-10-07 14:35 ` [PATCH v10 0/3] target/arm: Add FEAT_MEC to max cpu Peter Maydell
2025-10-10 11:40 ` Peter Maydell
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