From: Peter Maydell <peter.maydell@linaro.org>
To: Richard Henderson <rth@twiddle.net>
Cc: Patch Tracking <patches@linaro.org>, Michael Matz <matz@suse.de>,
Alexander Graf <agraf@suse.de>,
QEMU Developers <qemu-devel@nongnu.org>,
C Fontana <claudio.fontana@linaro.org>,
Dirk Mueller <dmueller@suse.de>,
Laurent Desnogues <laurent.desnogues@gmail.com>,
"kvmarm@lists.cs.columbia.edu" <kvmarm@lists.cs.columbia.edu>
Subject: Re: [Qemu-devel] [PATCH v2 08/12] target-arm: A64: add support for B and BL insns
Date: Wed, 4 Dec 2013 22:14:58 +0000 [thread overview]
Message-ID: <CAFEAcA_miP9aF8_5eBADEfDtqceCbWsSNCbob8hu1a3yBhTdDg@mail.gmail.com> (raw)
In-Reply-To: <529FA4BB.6030601@twiddle.net>
On 4 December 2013 21:55, Richard Henderson <rth@twiddle.net> wrote:
> On 12/05/2013 08:33 AM, Peter Maydell wrote:
>> @@ -680,6 +720,7 @@ void gen_intermediate_code_internal_a64(ARMCPU *cpu,
>> dc->condjmp = 0;
>>
>> dc->aarch64 = 1;
>> + dc->tmp_a64_count = 0;
>> dc->thumb = 0;
>> dc->bswap_code = 0;
>> dc->condexec_mask = 0;
>
> Still no initialization of ->tmp_a64[]?
It doesn't need initialization, does it? It's a static array, and we
fill it as new temps are requested. So all we need to do is clear
the count so it starts "empty". Or have I missed something?
thanks
-- PMM
next prev parent reply other threads:[~2013-12-04 22:15 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-12-04 19:33 [Qemu-devel] [PATCH v2 00/12] target-arm: A64 decoder, foundation plus branches Peter Maydell
2013-12-04 19:33 ` [Qemu-devel] [PATCH v2 01/12] target-arm: Split A64 from A32/T32 gen_intermediate_code_internal() Peter Maydell
2013-12-04 19:33 ` [Qemu-devel] [PATCH v2 02/12] target-arm: A64: add set_pc cpu method Peter Maydell
2013-12-04 19:33 ` [Qemu-devel] [PATCH v2 03/12] target-arm: A64: provide functions for accessing FPCR and FPSR Peter Maydell
2013-12-04 19:33 ` [Qemu-devel] [PATCH v2 04/12] target-arm: Support fp registers in gdb stub Peter Maydell
2013-12-04 19:33 ` [Qemu-devel] [PATCH v2 05/12] target-arm: A64: add stubs for a64 specific helpers Peter Maydell
2013-12-04 19:33 ` [Qemu-devel] [PATCH v2 06/12] target-arm: A64: provide skeleton for a64 insn decoding Peter Maydell
2013-12-04 19:33 ` [Qemu-devel] [PATCH v2 07/12] target-arm: A64: expand decoding skeleton for system instructions Peter Maydell
2013-12-04 19:33 ` [Qemu-devel] [PATCH v2 08/12] target-arm: A64: add support for B and BL insns Peter Maydell
2013-12-04 21:55 ` Richard Henderson
2013-12-04 22:14 ` Peter Maydell [this message]
2013-12-04 22:29 ` Richard Henderson
2013-12-04 22:43 ` Peter Maydell
2013-12-04 19:33 ` [Qemu-devel] [PATCH v2 09/12] target-arm: A64: add support for BR, BLR and RET insns Peter Maydell
2013-12-04 19:33 ` [Qemu-devel] [PATCH v2 10/12] target-arm: A64: add support for conditional branches Peter Maydell
2013-12-04 21:55 ` Richard Henderson
2013-12-04 19:33 ` [Qemu-devel] [PATCH v2 11/12] target-arm: A64: add support for 'test and branch' imm Peter Maydell
2013-12-04 21:56 ` Richard Henderson
2013-12-04 19:33 ` [Qemu-devel] [PATCH v2 12/12] target-arm: A64: add support for compare and branch imm Peter Maydell
2013-12-04 21:59 ` Richard Henderson
2013-12-04 22:19 ` Peter Maydell
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