From: Peter Maydell <peter.maydell@linaro.org>
To: Richard Henderson <richard.henderson@linaro.org>
Cc: qemu-arm <qemu-arm@nongnu.org>, QEMU Developers <qemu-devel@nongnu.org>
Subject: Re: [PATCH 3/4] target/arm: Take an exception if PC is misaligned
Date: Thu, 19 Aug 2021 20:24:06 +0100 [thread overview]
Message-ID: <CAFEAcA_p_sUJF2PFkmxS7LcB0ed_BtRC_VbF2WDP-eAPsZukNQ@mail.gmail.com> (raw)
In-Reply-To: <b6754a17-7b6a-201d-6c33-7759ea8ea270@linaro.org>
On Thu, 19 Aug 2021 at 17:57, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> On 8/19/21 6:50 AM, Richard Henderson wrote:
> > On 8/19/21 3:40 AM, Peter Maydell wrote:
> >>> uint32_t insn;
> >>> bool is_16bit;
> >>>
> >>> - if (arm_pre_translate_insn(dc)) {
> >>> + if (arm_check_ss_active(dc) || arm_check_kernelpage(dc)) {
> >>
> >>
> >> Is it not possible to get a misaligned PC in the Thumb case ?
> >
> > No. The thumb bit is always removed, leaving all pc aligned mod 2.
> > Both BXWritePC and BranchWritePC do this, as do we in gen_bx and store_reg.
>
> Do you think it's worth an assert here to make sure we never miss a case? I did an audit
> of the exception code and it looks like we mask everything correctly there, but...
(Did you check the M-profile code too? That also architecturally I think
should never let PC have the low bit set; hopefully the code I wrote
actually ensures that...)
I guess an assert() is more helpful than ploughing ahead with
a misaligned PC value. If we don't assert we should at least have
a comment saying misaligned Thumb PCs are architecturally impossible.
If we do go for the assert, then the comment in arm_cpu_gdb_write_register()
about why we don't let GDB set bit 0 in the PC would need updating (there
would now be two reasons). We should probably also fail the migration if
we get an unaligned Thumb PC in the inbound data.
-- PMM
next prev parent reply other threads:[~2021-08-19 19:25 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-18 1:00 [PATCH 0/4] target/arm: Fix insn exception priorities Richard Henderson
2021-08-18 1:00 ` [PATCH 1/4] target/arm: Take an exception if PSTATE.IL is set Richard Henderson
2021-08-18 1:00 ` [PATCH 2/4] target/arm: Merge disas_a64_insn into aarch64_tr_translate_insn Richard Henderson
2021-08-19 13:36 ` Peter Maydell
2021-08-18 1:00 ` [PATCH 3/4] target/arm: Take an exception if PC is misaligned Richard Henderson
2021-08-18 16:44 ` Richard Henderson
2021-08-19 13:40 ` Peter Maydell
2021-08-19 16:50 ` Richard Henderson
2021-08-19 16:57 ` Richard Henderson
2021-08-19 19:24 ` Peter Maydell [this message]
2021-08-19 20:34 ` Richard Henderson
2021-08-19 19:18 ` Peter Maydell
2021-08-19 19:46 ` Peter Maydell
2021-08-18 1:00 ` [PATCH 4/4] target/arm: Suppress bp for exceptions with more priority Richard Henderson
2021-08-19 13:48 ` Peter Maydell
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