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From: Peter Maydell <peter.maydell@linaro.org>
Date: Fri, 4 Sep 2015 14:59:47 +0100
Message-ID: <CAFEAcA_rHCvBqU_B5OLjR2o+aXvyRxZSDR4Kvso-sTdtz5oPSw@mail.gmail.com>
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Subject: Re: [Qemu-devel] [PATCH v2] target-arm: Break the TB after ISB to
 execute self-modified code correctly
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To: Sergey Sorokin <afarallax@yandex.ru>
Cc: QEMU Developers <qemu-devel@nongnu.org>

On 2 September 2015 at 11:03, Sergey Sorokin <afarallax@yandex.ru> wrote:
> If any store instruction writes the code inside the same TB
> after this store insn, the execution of the TB must be stopped
> to execute new code correctly.
> As described in ARMv8 manual D3.4.6 a self-modified code need to do
> IC invalidation to be valid, and ISB after it. So it's enough to end the TB
> after ISB instruction on the code translation.
>
> Signed-off-by: Sergey Sorokin <afarallax@yandex.ru>
> ---
> In the first version of the patch the TB was broken after IC invalidation
> instead of ISB.

This is correct code-wise as far as it goes, but:

(1) we should mention in the commit message and comments
both of the reasons for breaking the TB:

 /* Break the TB after an ISB:
  * (1) the architecture requires that we take any pending
  * interrupts immediately (v8 ARM ARM D1.14.4)
  * (2) self-modifying code might otherwise be changing a
  * later insn within the same TB as itself
  */

Also, you've missed the ARMv6 ISB which is within
v6_cp_reginfo[] as a cp15 instruction.

thanks
-- PMM