[PULL 0/3] tcg patch queue

[PULL 0/3] tcg patch queue

[Richard Henderson]

The following changes since commit e18e5501d8ac692d32657a3e1ef545b14e72b730:

  Merge remote-tracking branch 'remotes/dgilbert-gitlab/tags/pull-virtiofs-20200210' into staging (2020-02-10 18:09:14 +0000)

are available in the Git repository at:

  https://github.com/rth7680/qemu.git tags/pull-tcg-20200212

for you to fetch changes up to 2445971604c1cfd3ec484457159f4ac300fb04d2:

  tcg: Add tcg_gen_gvec_5_ptr (2020-02-12 14:58:36 -0800)

----------------------------------------------------------------
Fix breakpoint invalidation.
Add support for tcg helpers with 7 arguments.
Add support for gvec helpers with 5 arguments.

----------------------------------------------------------------
Max Filippov (1):
      exec: flush CPU TB cache in breakpoint_invalidate

Richard Henderson (1):
      tcg: Add tcg_gen_gvec_5_ptr

Taylor Simpson (1):
      tcg: Add support for a helper with 7 arguments

 include/exec/helper-gen.h   | 13 +++++++++++++
 include/exec/helper-head.h  |  2 ++
 include/exec/helper-proto.h |  6 ++++++
 include/exec/helper-tcg.h   |  7 +++++++
 include/tcg/tcg-op-gvec.h   |  7 +++++++
 exec.c                      | 15 +++++++--------
 tcg/tcg-op-gvec.c           | 32 ++++++++++++++++++++++++++++++++
 7 files changed, 74 insertions(+), 8 deletions(-)

Re: [PULL 0/3] tcg patch queue

[Peter Maydell]

On Thu, 13 Feb 2020 at 00:23, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> The following changes since commit e18e5501d8ac692d32657a3e1ef545b14e72b730:
>
>   Merge remote-tracking branch 'remotes/dgilbert-gitlab/tags/pull-virtiofs-20200210' into staging (2020-02-10 18:09:14 +0000)
>
> are available in the Git repository at:
>
>   https://github.com/rth7680/qemu.git tags/pull-tcg-20200212
>
> for you to fetch changes up to 2445971604c1cfd3ec484457159f4ac300fb04d2:
>
>   tcg: Add tcg_gen_gvec_5_ptr (2020-02-12 14:58:36 -0800)
>
> ----------------------------------------------------------------
> Fix breakpoint invalidation.
> Add support for tcg helpers with 7 arguments.
> Add support for gvec helpers with 5 arguments.
>


Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/5.0
for any user-visible changes.

-- PMM

[PULL 0/3] tcg patch queue

[Richard Henderson]

The following changes since commit 4a74626970ab4ea475263d155b10fb75c9af0b33:

  Merge remote-tracking branch 'remotes/stefanha-gitlab/tags/tracing-pull-request' into staging (2020-10-27 11:28:46 +0000)

are available in the Git repository at:

  https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20201027

for you to fetch changes up to 1d705e8a5bbfe36294081baa45ab68a9ad987f33:

  accel/tcg: Add CPU_LOG_EXEC tracing for cpu_io_recompile() (2020-10-27 09:48:07 -0700)

----------------------------------------------------------------
Optimize across branches.
Add logging for cpu_io_recompile.

----------------------------------------------------------------
Peter Maydell (1):
      accel/tcg: Add CPU_LOG_EXEC tracing for cpu_io_recompile()

Richard Henderson (2):
      tcg: Do not kill globals at conditional branches
      tcg/optimize: Flush data at labels not TCG_OPF_BB_END

 include/tcg/tcg-opc.h     |  7 +++---
 include/tcg/tcg.h         |  4 +++-
 accel/tcg/translate-all.c |  4 ++++
 tcg/optimize.c            | 35 +++++++++++++++---------------
 tcg/tcg.c                 | 55 +++++++++++++++++++++++++++++++++++++++++++++--
 5 files changed, 82 insertions(+), 23 deletions(-)

Re: [PULL 0/3] tcg patch queue

[Peter Maydell]

On Tue, 27 Oct 2020 at 16:51, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> The following changes since commit 4a74626970ab4ea475263d155b10fb75c9af0b33:
>
>   Merge remote-tracking branch 'remotes/stefanha-gitlab/tags/tracing-pull-request' into staging (2020-10-27 11:28:46 +0000)
>
> are available in the Git repository at:
>
>   https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20201027
>
> for you to fetch changes up to 1d705e8a5bbfe36294081baa45ab68a9ad987f33:
>
>   accel/tcg: Add CPU_LOG_EXEC tracing for cpu_io_recompile() (2020-10-27 09:48:07 -0700)
>
> ----------------------------------------------------------------
> Optimize across branches.
> Add logging for cpu_io_recompile.
>
> ----------------------------------------------------------------
> Peter Maydell (1):
>       accel/tcg: Add CPU_LOG_EXEC tracing for cpu_io_recompile()
>
> Richard Henderson (2):
>       tcg: Do not kill globals at conditional branches
>       tcg/optimize: Flush data at labels not TCG_OPF_BB_END


Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/5.2
for any user-visible changes.

-- PMM

Re: [PULL 0/3] tcg patch queue

[Peter Maydell]

On Tue, 27 Oct 2020 at 16:51, Richard Henderson
<richard.henderson@linaro.org> wrote:
> ----------------------------------------------------------------
> Optimize across branches.
> Add logging for cpu_io_recompile.

Igor2 reported on IRC that this seems to cause a crash when
using an hppa guest. This is apparently happening on a proprietary
disk image, so no reproducible test case, but the logging of
the tail end of -d in_asm,op is at:
 http://igor2.repo.hu/tmp/in_asm_op.log

QEMU asserts with
../tcg/tcg.c:3346: tcg fatal error

The TB in question involves several conditional branches; the
generated TCG ops look OK to me, and reverting the two commits
b4cb76e6208cf6b5b and cd0372c515c4732d8b fixes the crash.
(We didn't test reverting only one of the two commits separately.)

thanks
-- PMM

Re: [PULL 0/3] tcg patch queue

[Richard Henderson]

On 11/2/20 5:57 AM, Peter Maydell wrote:
> On Tue, 27 Oct 2020 at 16:51, Richard Henderson
> <richard.henderson@linaro.org> wrote:
>> ----------------------------------------------------------------
>> Optimize across branches.
>> Add logging for cpu_io_recompile.
> 
> Igor2 reported on IRC that this seems to cause a crash when
> using an hppa guest. This is apparently happening on a proprietary
> disk image, so no reproducible test case, but the logging of
> the tail end of -d in_asm,op is at:
>  http://igor2.repo.hu/tmp/in_asm_op.log
> 
> QEMU asserts with
> ../tcg/tcg.c:3346: tcg fatal error
> 
> The TB in question involves several conditional branches; the
> generated TCG ops look OK to me, and reverting the two commits
> b4cb76e6208cf6b5b and cd0372c515c4732d8b fixes the crash.
> (We didn't test reverting only one of the two commits separately.)

Ok, thanks, I'll look into it.


r~

[PULL 0/3] tcg patch queue

[Richard Henderson]

The following changes since commit 2ecfc0657afa5d29a373271b342f704a1a3c6737:

  Merge remote-tracking branch 'remotes/armbru/tags/pull-misc-2020-12-10' into staging (2020-12-10 17:01:05 +0000)

are available in the Git repository at:

  https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20201210

for you to fetch changes up to 9e2658d62ebc23efe7df43fc0e306f129510d874:

  accel/tcg: rename tcg-cpus functions to match module name (2020-12-10 17:44:10 -0600)

----------------------------------------------------------------
Split CpusAccel for tcg variants

----------------------------------------------------------------
Claudio Fontana (3):
      accel/tcg: split CpusAccel into three TCG variants
      accel/tcg: split tcg_start_vcpu_thread
      accel/tcg: rename tcg-cpus functions to match module name

 accel/tcg/tcg-cpus-icount.h |  17 ++
 accel/tcg/tcg-cpus-rr.h     |  21 ++
 accel/tcg/tcg-cpus.h        |  12 +-
 accel/tcg/tcg-all.c         |  13 +-
 accel/tcg/tcg-cpus-icount.c | 147 +++++++++++++
 accel/tcg/tcg-cpus-mttcg.c  | 140 ++++++++++++
 accel/tcg/tcg-cpus-rr.c     | 305 ++++++++++++++++++++++++++
 accel/tcg/tcg-cpus.c        | 506 +-------------------------------------------
 softmmu/icount.c            |   2 +-
 accel/tcg/meson.build       |   9 +-
 10 files changed, 670 insertions(+), 502 deletions(-)
 create mode 100644 accel/tcg/tcg-cpus-icount.h
 create mode 100644 accel/tcg/tcg-cpus-rr.h
 create mode 100644 accel/tcg/tcg-cpus-icount.c
 create mode 100644 accel/tcg/tcg-cpus-mttcg.c
 create mode 100644 accel/tcg/tcg-cpus-rr.c

Re: [PULL 0/3] tcg patch queue

[Peter Maydell]

On Fri, 11 Dec 2020 at 01:10, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> The following changes since commit 2ecfc0657afa5d29a373271b342f704a1a3c6737:
>
>   Merge remote-tracking branch 'remotes/armbru/tags/pull-misc-2020-12-10' into staging (2020-12-10 17:01:05 +0000)
>
> are available in the Git repository at:
>
>   https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20201210
>
> for you to fetch changes up to 9e2658d62ebc23efe7df43fc0e306f129510d874:
>
>   accel/tcg: rename tcg-cpus functions to match module name (2020-12-10 17:44:10 -0600)
>
> ----------------------------------------------------------------
> Split CpusAccel for tcg variants
>
> ----------------------------------------------------------------


Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/6.0
for any user-visible changes.

-- PMM

[PULL 0/3] tcg patch queue

[Richard Henderson]

The following changes since commit 41192db338588051f21501abc13743e62b0a5605:

  Merge remote-tracking branch 'remotes/ehabkost-gl/tags/machine-next-pull-request' into staging (2021-01-01 22:57:15 +0000)

are available in the Git repository at:

  https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20210104

for you to fetch changes up to a66424ba17d661007dc13d78c9e3014ccbaf0efb:

  tcg: Add tcg_gen_bswap_tl alias (2021-01-04 06:32:58 -1000)

----------------------------------------------------------------
Fix vector clear issue.
Fix riscv host shift issue.
Add tcg_gen_bswap_tl.

----------------------------------------------------------------
Richard Henderson (2):
      tcg: Use memset for large vector byte replication
      tcg: Add tcg_gen_bswap_tl alias

Zihao Yu (1):
      tcg/riscv: Fix illegal shift instructions

 accel/tcg/tcg-runtime.h     | 11 +++++++++++
 include/exec/helper-proto.h |  4 ++++
 include/tcg/tcg-op.h        |  2 ++
 tcg/tcg-op-gvec.c           | 32 ++++++++++++++++++++++++++++++++
 tcg/riscv/tcg-target.c.inc  | 12 ++++++------
 5 files changed, 55 insertions(+), 6 deletions(-)

Re: [PULL 0/3] tcg patch queue

[Peter Maydell]

On Mon, 4 Jan 2021 at 17:35, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> The following changes since commit 41192db338588051f21501abc13743e62b0a5605:
>
>   Merge remote-tracking branch 'remotes/ehabkost-gl/tags/machine-next-pull-request' into staging (2021-01-01 22:57:15 +0000)
>
> are available in the Git repository at:
>
>   https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20210104
>
> for you to fetch changes up to a66424ba17d661007dc13d78c9e3014ccbaf0efb:
>
>   tcg: Add tcg_gen_bswap_tl alias (2021-01-04 06:32:58 -1000)
>
> ----------------------------------------------------------------
> Fix vector clear issue.
> Fix riscv host shift issue.
> Add tcg_gen_bswap_tl.


Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/6.0
for any user-visible changes.

-- PMM

[PULL 0/3] tcg patch queue

[Richard Henderson]

The following changes since commit 00483d386901173e84c7965f9f0d678791a75e01:

  Merge remote-tracking branch 'remotes/shorne/tags/or1k-pull-request' into staging (2022-02-28 11:27:16 +0000)

are available in the Git repository at:

  https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20220228

for you to fetch changes up to 2ccf40f00e3f29d85d4ff48a9a98870059002290:

  tcg/tci: Use tcg_out_ldst in tcg_out_st (2022-02-28 08:04:10 -1000)

----------------------------------------------------------------
Fix typecode generation for tcg helpers
Fix single stepping into interrupt handlers
Fix out-of-range offsets for stores in TCI

----------------------------------------------------------------
Luc Michel (1):
      accel/tcg/cpu-exec: Fix precise single-stepping after interrupt

Richard Henderson (2):
      tcg: Remove dh_alias indirection for dh_typecode
      tcg/tci: Use tcg_out_ldst in tcg_out_st

 include/exec/helper-head.h   | 19 ++++++++++---------
 target/hppa/helper.h         |  2 ++
 target/i386/ops_sse_header.h |  3 +++
 target/m68k/helper.h         |  1 +
 target/ppc/helper.h          |  3 +++
 accel/tcg/cpu-exec.c         |  8 ++++++--
 tcg/tci/tcg-target.c.inc     |  5 ++---
 7 files changed, 27 insertions(+), 14 deletions(-)

[PULL 1/3] tcg: Remove dh_alias indirection for dh_typecode

[Richard Henderson]

The dh_alias redirect is intended to handle TCG types as distinguished
from C types.  TCG does not distinguish signed int from unsigned int,
because they are the same size.  However, we need to retain this
distinction for dh_typecode, lest we fail to extend abi types properly
for the host call parameters.

This bug was detected when running the 'arm' emulator on an s390
system. The s390 uses TCG_TARGET_EXTEND_ARGS which triggers code
in tcg_gen_callN to extend 32 bit values to 64 bits; the incorrect
sign data in the typemask for each argument caused the values to be
extended as unsigned values.

This simple program exhibits the problem:

	static volatile int num = -9;
	static volatile int den = -5;
	int main(void)
	{
		int quo = num / den;
		printf("num %d den %d quo %d\n", num, den, quo);
		exit(0);
	}

When run on the broken qemu, this results in:

	num -9 den -5 quo 0

The correct result is:

	num -9 den -5 quo 1

Fixes: 7319d83a735 ("tcg: Combine dh_is_64bit and dh_is_signed to dh_typecode")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/876
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reported-by: Christian Ehrhardt <christian.ehrhardt@canonical.com>
Tested-by: Christian Ehrhardt <christian.ehrhardt@canonical.com>
Tested-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 include/exec/helper-head.h   | 19 ++++++++++---------
 target/hppa/helper.h         |  2 ++
 target/i386/ops_sse_header.h |  3 +++
 target/m68k/helper.h         |  1 +
 target/ppc/helper.h          |  3 +++
 5 files changed, 19 insertions(+), 9 deletions(-)

diff --git a/include/exec/helper-head.h b/include/exec/helper-head.h
index b974eb394a..734af067fe 100644
--- a/include/exec/helper-head.h
+++ b/include/exec/helper-head.h
@@ -53,13 +53,16 @@
 # ifdef TARGET_LONG_BITS
 #  if TARGET_LONG_BITS == 32
 #   define dh_alias_tl i32
+#   define dh_typecode_tl dh_typecode_i32
 #  else
 #   define dh_alias_tl i64
+#   define dh_typecode_tl dh_typecode_i64
 #  endif
 # endif
-# define dh_alias_env ptr
 # define dh_ctype_tl target_ulong
+# define dh_alias_env ptr
 # define dh_ctype_env CPUArchState *
+# define dh_typecode_env dh_typecode_ptr
 #endif
 
 /* We can't use glue() here because it falls foul of C preprocessor
@@ -92,18 +95,16 @@
 #define dh_typecode_i64 4
 #define dh_typecode_s64 5
 #define dh_typecode_ptr 6
-#define dh_typecode(t) glue(dh_typecode_, dh_alias(t))
+#define dh_typecode_int dh_typecode_s32
+#define dh_typecode_f16 dh_typecode_i32
+#define dh_typecode_f32 dh_typecode_i32
+#define dh_typecode_f64 dh_typecode_i64
+#define dh_typecode_cptr dh_typecode_ptr
+#define dh_typecode(t) dh_typecode_##t
 
 #define dh_callflag_i32  0
-#define dh_callflag_s32  0
-#define dh_callflag_int  0
 #define dh_callflag_i64  0
-#define dh_callflag_s64  0
-#define dh_callflag_f16  0
-#define dh_callflag_f32  0
-#define dh_callflag_f64  0
 #define dh_callflag_ptr  0
-#define dh_callflag_cptr dh_callflag_ptr
 #define dh_callflag_void 0
 #define dh_callflag_noreturn TCG_CALL_NO_RETURN
 #define dh_callflag(t) glue(dh_callflag_, dh_alias(t))
diff --git a/target/hppa/helper.h b/target/hppa/helper.h
index fe8a9ce493..c7e35ce8c7 100644
--- a/target/hppa/helper.h
+++ b/target/hppa/helper.h
@@ -1,7 +1,9 @@
 #if TARGET_REGISTER_BITS == 64
 # define dh_alias_tr     i64
+# define dh_typecode_tr  dh_typecode_i64
 #else
 # define dh_alias_tr     i32
+# define dh_typecode_tr  dh_typecode_i32
 #endif
 #define dh_ctype_tr      target_ureg
 
diff --git a/target/i386/ops_sse_header.h b/target/i386/ops_sse_header.h
index e68af5c403..cef28f2aae 100644
--- a/target/i386/ops_sse_header.h
+++ b/target/i386/ops_sse_header.h
@@ -30,6 +30,9 @@
 #define dh_ctype_Reg Reg *
 #define dh_ctype_ZMMReg ZMMReg *
 #define dh_ctype_MMXReg MMXReg *
+#define dh_typecode_Reg dh_typecode_ptr
+#define dh_typecode_ZMMReg dh_typecode_ptr
+#define dh_typecode_MMXReg dh_typecode_ptr
 
 DEF_HELPER_3(glue(psrlw, SUFFIX), void, env, Reg, Reg)
 DEF_HELPER_3(glue(psraw, SUFFIX), void, env, Reg, Reg)
diff --git a/target/m68k/helper.h b/target/m68k/helper.h
index 9842eeaa95..0a6b4146f6 100644
--- a/target/m68k/helper.h
+++ b/target/m68k/helper.h
@@ -17,6 +17,7 @@ DEF_HELPER_4(cas2l_parallel, void, env, i32, i32, i32)
 
 #define dh_alias_fp ptr
 #define dh_ctype_fp FPReg *
+#define dh_typecode_fp dh_typecode_ptr
 
 DEF_HELPER_3(exts32, void, env, fp, s32)
 DEF_HELPER_3(extf32, void, env, fp, f32)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index ab008c9d4e..ae7d503fcf 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -127,9 +127,11 @@ DEF_HELPER_FLAGS_1(ftsqrt, TCG_CALL_NO_RWG_SE, i32, i64)
 
 #define dh_alias_avr ptr
 #define dh_ctype_avr ppc_avr_t *
+#define dh_typecode_avr dh_typecode_ptr
 
 #define dh_alias_vsr ptr
 #define dh_ctype_vsr ppc_vsr_t *
+#define dh_typecode_vsr dh_typecode_ptr
 
 DEF_HELPER_3(vavgub, void, avr, avr, avr)
 DEF_HELPER_3(vavguh, void, avr, avr, avr)
@@ -708,6 +710,7 @@ DEF_HELPER_3(store_dbatu, void, env, i32, tl)
 
 #define dh_alias_fprp ptr
 #define dh_ctype_fprp ppc_fprp_t *
+#define dh_typecode_fprp dh_typecode_ptr
 
 DEF_HELPER_4(DADD, void, env, fprp, fprp, fprp)
 DEF_HELPER_4(DADDQ, void, env, fprp, fprp, fprp)
-- 
2.25.1

[PULL 2/3] accel/tcg/cpu-exec: Fix precise single-stepping after interrupt

[Richard Henderson]

From: Luc Michel <lmichel@kalray.eu>

In some cases, cpu->exit_request can be false after handling the
interrupt, leading to another TB being executed instead of returning
to the main loop.

Fix this by returning true unconditionally when in single-step mode.

Fixes: ba3c35d9c402 ("tcg/cpu-exec: precise single-stepping after an interrupt")
Signed-off-by: Luc Michel <lmichel@kalray.eu>
Message-Id: <20220214132656.11397-1-lmichel@kalray.eu>
[rth: Unlock iothread mutex; simplify indentation]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 accel/tcg/cpu-exec.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
index 8da6a55593..c68270f794 100644
--- a/accel/tcg/cpu-exec.c
+++ b/accel/tcg/cpu-exec.c
@@ -799,8 +799,12 @@ static inline bool cpu_handle_interrupt(CPUState *cpu,
                  * raised when single-stepping so that GDB doesn't miss the
                  * next instruction.
                  */
-                cpu->exception_index =
-                    (cpu->singlestep_enabled ? EXCP_DEBUG : -1);
+                if (unlikely(cpu->singlestep_enabled)) {
+                    cpu->exception_index = EXCP_DEBUG;
+                    qemu_mutex_unlock_iothread();
+                    return true;
+                }
+                cpu->exception_index = -1;
                 *last_tb = NULL;
             }
             /* The target hook may have updated the 'cpu->interrupt_request';
-- 
2.25.1

[PULL 3/3] tcg/tci: Use tcg_out_ldst in tcg_out_st

[Richard Henderson]

The tcg_out_ldst helper will handle out-of-range offsets.
We haven't actually encountered any, since we haven't run
across the assert within tcg_out_op_rrs, but an out-of-range
offset would not be impossible in future.

Fixes: 65089889183 ("tcg/tci: Change encoding to uint32_t units")
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/tci/tcg-target.c.inc | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index 0cb16aaa81..9ff1fa0832 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -790,14 +790,13 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
 static void tcg_out_st(TCGContext *s, TCGType type, TCGReg val, TCGReg base,
                        intptr_t offset)
 {
-    stack_bounds_check(base, offset);
     switch (type) {
     case TCG_TYPE_I32:
-        tcg_out_op_rrs(s, INDEX_op_st_i32, val, base, offset);
+        tcg_out_ldst(s, INDEX_op_st_i32, val, base, offset);
         break;
 #if TCG_TARGET_REG_BITS == 64
     case TCG_TYPE_I64:
-        tcg_out_op_rrs(s, INDEX_op_st_i64, val, base, offset);
+        tcg_out_ldst(s, INDEX_op_st_i64, val, base, offset);
         break;
 #endif
     default:
-- 
2.25.1

Re: [PULL 0/3] tcg patch queue

[Peter Maydell]

On Mon, 28 Feb 2022 at 18:09, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> The following changes since commit 00483d386901173e84c7965f9f0d678791a75e01:
>
>   Merge remote-tracking branch 'remotes/shorne/tags/or1k-pull-request' into staging (2022-02-28 11:27:16 +0000)
>
> are available in the Git repository at:
>
>   https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20220228
>
> for you to fetch changes up to 2ccf40f00e3f29d85d4ff48a9a98870059002290:
>
>   tcg/tci: Use tcg_out_ldst in tcg_out_st (2022-02-28 08:04:10 -1000)
>
> ----------------------------------------------------------------
> Fix typecode generation for tcg helpers
> Fix single stepping into interrupt handlers
> Fix out-of-range offsets for stores in TCI
>
> ----------------------------------------------------------------


Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/7.0
for any user-visible changes.

-- PMM

[PULL 0/3] tcg patch queue

[Richard Henderson]

The following changes since commit 1e62a82574fc28e64deca589a23cf55ada2e1a7d:

  Merge tag 'm68k-for-7.1-pull-request' of https://github.com/vivier/qemu-m68k into staging (2022-06-02 06:30:24 -0700)

are available in the Git repository at:

  https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20220602

for you to fetch changes up to 94bcc91b2e95e02ec57ed18d5a5e7cb75aa19a50:

  tcg/aarch64: Fix illegal insn from out-of-range shli (2022-06-02 08:09:46 -0700)

----------------------------------------------------------------
Add tcg_gen_mov_ptr.
Fix tcg/i386 encoding of avx512 vpsraq.
Fix tcg/aarch64 handling of out-of-range shli.

----------------------------------------------------------------
Richard Henderson (3):
      tcg: Add tcg_gen_mov_ptr
      tcg/i386: Fix encoding of OPC_VPSRAQ for INDEX_op_sars_vec
      tcg/aarch64: Fix illegal insn from out-of-range shli

 include/tcg/tcg-op.h         | 5 +++++
 tcg/aarch64/tcg-target.c.inc | 2 +-
 tcg/i386/tcg-target.c.inc    | 2 +-
 3 files changed, 7 insertions(+), 2 deletions(-)

Re: [PULL 0/3] tcg patch queue

[Richard Henderson]

On 6/2/22 08:13, Richard Henderson wrote:
> The following changes since commit 1e62a82574fc28e64deca589a23cf55ada2e1a7d:
> 
>    Merge tag 'm68k-for-7.1-pull-request' of https://github.com/vivier/qemu-m68k into staging (2022-06-02 06:30:24 -0700)
> 
> are available in the Git repository at:
> 
>    https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20220602
> 
> for you to fetch changes up to 94bcc91b2e95e02ec57ed18d5a5e7cb75aa19a50:
> 
>    tcg/aarch64: Fix illegal insn from out-of-range shli (2022-06-02 08:09:46 -0700)
> 
> ----------------------------------------------------------------
> Add tcg_gen_mov_ptr.
> Fix tcg/i386 encoding of avx512 vpsraq.
> Fix tcg/aarch64 handling of out-of-range shli.

Applied, thanks.  Please update https://wiki.qemu.org/ChangeLog/7.1 as appropriate.


r~



> 
> ----------------------------------------------------------------
> Richard Henderson (3):
>        tcg: Add tcg_gen_mov_ptr
>        tcg/i386: Fix encoding of OPC_VPSRAQ for INDEX_op_sars_vec
>        tcg/aarch64: Fix illegal insn from out-of-range shli
> 
>   include/tcg/tcg-op.h         | 5 +++++
>   tcg/aarch64/tcg-target.c.inc | 2 +-
>   tcg/i386/tcg-target.c.inc    | 2 +-
>   3 files changed, 7 insertions(+), 2 deletions(-)